Base Platform Changes - 2023.1 English

Vitis Tutorials: AI Engine Development

Document ID
Release Date
2023.1 English

The AMD Vivado™ tools design needs to be modified to have the AI Engine domain mapped into the RPU address space. The AMD Versal™ adaptive SoC real-time processing unit (RPU) is a 32-bit processor, but addressing the AI Engine requires at least 44 bits. This issue can be resolved using the address remap capability of the NoC NMU.

To do this, run the following commands in the Tcl console:

set_property CONFIG.REMAPS {{M00_AXI {{0x4000_0000 0x200_0000_0000 1G}}}} [get_bd_intf_pins /ps_noc/S01_AXI]
set_property range 1G [get_bd_addr_segs {versal_cips_0/DATA_RPU0/SEG_ps_noc_C0_DDR_LOW0}]
assign_bd_address -offset 0x40000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_RPU0] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force

After the block design passes validation, regenerate the output and export the platform XSA file.