Build XCLBIN from Scratch - 2023.2 English

Vitis Tutorials: AI Engine (XD100)

Document ID
XD100
Release Date
2024-03-05
Version
2023.2 English

Building the XCLBINs from scratch takes about 16 hours to complete. To create the Vitis compiler linker output from scratch, start the builds with the following commands:

make xsa_all

or

make xclbin TARGET=hw REV=rev0          #fails timing
make xclbin TARGET=hw REV=rev1          #passes timing
make xclbin TARGET=hw_emu REV=rev1      #create for hardware emulation

or

mkdir build/rev0/hw
cd build/rev0/hw
v++ -l                                                  \
    -t hw                                               \
    -f ../../../Module_01_Custom_Platform/build/sw/vck190_v1_0/export/vck190_v1_0/vck190_v1_0.xpfm  \
    --save-temps                                        \
    -g                                                  \
    ../../Module_02_AI_Engine_Design/libadf.a           \
    ../../Module_03_PL_Design/ip_repo/dlbf_slave.xo     \
    ../../Module_03_PL_Design/ip_repo/dlbf_data.xo      \
    ../../Module_03_PL_Design/ip_repo/dlbf_coeffs.xo    \
    ../../Module_03_PL_Design/ip_repo/ulbf_slave.xo     \
    ../../Module_03_PL_Design/ip_repo/ulbf_data.xo      \
    ../../Module_03_PL_Design/ip_repo/ulbf_coeffs.xo    \
    --config ../../../config.ini                        \
    -o beamforming.rev0.hw.xclbin

cd ../../../
mkdir build/rev1/hw
cd build/rev1/hw
v++ -l                                                  \
    -t hw                                               \
    -f ../../../Module_01_Custom_Platform/build/sw/vck190_v1_0/export/vck190_v1_0/vck190_v1_0.xpfm  \
    --save-temps                                        \
    -g                                                  \
    ../../Module_02_AI_Engine_Design/libadf.a           \
    ../../Module_03_PL_Design/ip_repo/dlbf_slave.xo     \
    ../../Module_03_PL_Design/ip_repo/dlbf_data.xo      \
    ../../Module_03_PL_Design/ip_repo/dlbf_coeffs.xo    \
    ../../Module_03_PL_Design/ip_repo/ulbf_slave.xo     \
    ../../Module_03_PL_Design/ip_repo/ulbf_data.xo      \
    ../../Module_03_PL_Design/ip_repo/ulbf_coeffs.xo    \
    --config ../../../config_2regslice.ini              \
    -o beamforming.rev1.hw.xclbin

cd ../../../
mkdir build/rev1/hw_emu
cd build/rev1/hw_emu
v++ -l                                                  \
    -t hw_emu                                           \
    -f ../../../Module_01_Custom_Platform/build/sw/vck190_v1_0/export/vck190_v1_0/vck190_v1_0.xpfm  \
    --save-temps                                        \
    -g                                                  \
    ../../Module_02_AI_Engine_Design/libadf.a           \
    ../../Module_03_PL_Design/ip_repo/dlbf_slave.xo     \
    ../../Module_03_PL_Design/ip_repo/dlbf_data.xo      \
    ../../Module_03_PL_Design/ip_repo/dlbf_coeffs.xo    \
    ../../Module_03_PL_Design/ip_repo/ulbf_slave.xo     \
    ../../Module_03_PL_Design/ip_repo/ulbf_data.xo      \
    ../../Module_03_PL_Design/ip_repo/ulbf_coeffs.xo    \
    --config ../../../config_2regslice.ini              \
    -o beamforming.rev1.hw_emu.xclbin