The next step is to connect the output clocks of the Clocking Wizard to the rest of the design. First, connect the Clocking Wizard’s output clock 6 (100 MHz) to the AXI Debug Hub IP and the NoC PL clock (aclk5). Sync the Processor Reset System #6 to this clock as well. Also, connect the asynchronous reset of the AXI Debug Hub IP to the Processor Reset System #6.
Next, connect the Clocking Wizard’s output clock 1 (250MHz) to the ctrl_sm, the 16 AXI SmartConnects, 16 AXI Verification IPs, and the CIPS’ m_axi_fpd_aclk. Sync the Processor Reset System #1 to this clock as well.
Sync the rest of the Processor Reset Systems (#2, 3, 4, and 5) to the Clocking Wizard’s output clocks (clock output 2 = 500 MHz, clock output 3 = 400 MHz, clock output 4 = 450 MHz, and clock output 5 = 250 MHz).
Connect the Clocking Wizard’s locked pin to the dcm_locked pins of the Processor Reset Systems.
Connect the CIPS’ pl0_ref_clk as the input to the Clocking Wizard (clk_in1).
Lastly, connect the CIPs’ pl0_resetn as the input to the ext_reset_in pins of Processor Reset Systems.