Navigate to the MultiKernel directory. In the Makefile, three methods are defined:
aieCompiles the graph and the kernels
aie_simRuns the AI Engine System C simulator
aie_vizRuns
vitis_analyzeron the output summary
Take a look at the source code (kernel and graph) to familiarize yourself with C++ instantiation of kernels. In graph.cpp, the PL AI Engine connections are declared using 64-bit interfaces running at 500 MHz, allowing for maximum bandwidth on the AI Engine array AXI-Stream network.
To have the simulation running, input data must be generated. There are two possibilities:
Just type
make data.Change directory to
dataand typeGenerateStreamsGUI. The following parameters should be set for this example:
Click Generate and then Exit. The generated files PhaseIn_0_0.txt … PhaseIn_7_7.txt should contain mainly 0’s, with a few 1’s and 2’s. The number of samples per stream is half of the one that is declared in the C++ code because in the C++ code this is the length of the concatenation of both input streams.
Type make all and wait for the vitis_analyzer GUI to Display. The AMD Vitis™ analyzer is able to show the graph, how it has been implemented in the device, and the complete timeline of the simulation. In this specific case, the graph is simple (a single kernel) and the implementation is on a single AI Engine.
Click Graph to visualize the graph of the application:
The 64 kernels and their 16 independent input streams are clearly visible. The top graph is for the output phases 0, 2, 4, and 6, the phases where the cascade stream goes from left to right on the physical device, and the bottom graph is for the phases 1, 3, 5, and 7 where the cascade stream goes from right to left.
Click Array to visualize where the kernel has been placed, and how it is fed from the the PL:
In this view, the cascade streams connecting neighboring AI Engines are key to the performance of this graph. With the four location constraints that were added, the placer had only one solution for the kernel placement: this square. The router had an easy job to feed all these kernels by simply using the south-north AXI-Stream. The path back to the PL from the extremities also uses only the vertical AXI-Streams.
Finally, click Trace to look at how the entire simulation went through. This may be useful to track where your AI Engine stalls if the performance is not as expected:
Now the output of the filter can be displayed. The input being a set of Dirac impulses, the impulse response of the filter should be recognized throughout the waveform. Navigate to Emulation-AIE/aiesimulator_output/data and look at the PhaseOut_0.txt. You can see that you have two complex outputs per line, which is prepended with a time stamp. ProcessAIEOutput PhaseOut_*.
The top graph reflects the real part of the output, the bottom graph this is the imaginary part. On both, the filter impulse response is recognizable.
The performance of this architecture can be measured using the timestamped output. In the same directory (Emulation-AIE/aiesimulator_output/data), type StreamThroughput PhaseOut_*:
PhaseOut_0_0.txt --> 1174.31 Msps
PhaseOut_0_1.txt --> 1170.02 Msps
PhaseOut_1_0.txt --> 1178.64 Msps
PhaseOut_1_1.txt --> 1172.16 Msps
PhaseOut_2_0.txt --> 1174.31 Msps
PhaseOut_2_1.txt --> 1170.02 Msps
PhaseOut_3_0.txt --> 1178.64 Msps
PhaseOut_3_1.txt --> 1172.16 Msps
PhaseOut_4_0.txt --> 1174.31 Msps
PhaseOut_4_1.txt --> 1170.02 Msps
PhaseOut_5_0.txt --> 1178.64 Msps
PhaseOut_5_1.txt --> 1172.16 Msps
PhaseOut_6_0.txt --> 1174.31 Msps
PhaseOut_6_1.txt --> 1170.02 Msps
PhaseOut_7_0.txt --> 1178.64 Msps
PhaseOut_7_1.txt --> 1172.16 Msps
-----------------------
Total Throughput --> 18780.51 Msps
This architecture achieves almost 19 Gsps performance. It is less than the maximum expected (20 Gsps) because of the number of cycles spent for initialization when the kernels are called. This performance increases when the frame length is increased. For a 32K sample frame length, the performance obtained is:
Total Throughput --> 19950.30 Msps
which is almost the expected maximum.