To work with externel traffic generators in hardware emulation,introduce hooks in the PL. For that purpose, Xilinx provides a complete set of XO files with various bitwidths in $XILINX_VITIS/data/emulation/XO :
sim_ipc_axis_master_NNN.xo with NNN in 8,16,32,64,128,256,512
sim_ipc_axis_slave_NNN.xo with NNN in 8,16,32,64,128,256,512
In this tutorial, 64 bit interfaces are required.