v++ lets you integrate your AI Engine, HLS, and RTL kernels into an existing extensible platform. This step is where the platform chosen is provided by the hardware designer (or you can opt to use one of the many extensible base platforms provided by Xilinx) and
v++ builds the hardware design for you in addition to integrating the AI Engine and PL kernels in the design.
You have a number of kernels at your disposal, but you need to tell the linker how you want to connect them together (from the AI Engine array to PL and vice versa). These connections are described in a configuration file:
system.cfg in this tutorial.
[connectivity] nk=sim_ipc_axis_master_64:1:tx_iqdata nk=sim_ipc_axis_slave_64:1:rx_iqdata stream_connect=tx_iqdata.M00_AXIS:ai_engine_0.DataIn stream_connect=ai_engine_0.DataOut:rx_iqdata.S00_AXIS
If additional master and slave traffic generator interfaces are required, change the “1” (between the sim_ipc_axis and the instance name) instead of instantiating more new kernels with the
ai_engine_0 the names are provided in the
graph.cpp when instantiating a
PLIO object. For this design, as an example, this line
PLIO *in0 = new PLIO("DataIn1", adf::plio_32_bits,"data/input.txt"); has the name DataIn1 which is the interface name.
You can see the
v++ switches in more detail in the Vitis Unified Software Platform Documentation.
To build the design, run the following command:
This will likely take more than 5 or 10 minutes.