Control Interfaces Requirements - 2023.2 English

Vitis Tutorials: AI Engine

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2023.2 English

Every platform must declare at least one general purpose AXI master port (M_AXI_GP). For each of the 16 AXI SmartConnects, 15 M_AXI_GP interfaces have been declared. Additionally, there is a M_AXI_NoC control interface on the NoC. These interfaces are used by the Vitis linker step to connect the PL kernels to the platform.