Create Block Design - 2023.2 English

Vitis Tutorials: AI Engine

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2023.2 English

The vck_190_v1_0_xsa.tcl script then calls the script, which generates the platform block design. Open the block design in the Vivado project located at hw/build/vck190_v1_0_vivado/vck190_v1_0.xpr. Note that there are five major components to the hardware platform: the AI Engine, CIPS, NoC (Network-on-Chip), Clocking Wizard IP, Clock Reset IPs, 16 AXI4-LITE SmartConnect interfaces, and a top-level AXI4-Lite SmartConnect (called ctrl_sm).

Platform Block Design

Open the file and review the comments. After the Setup and Error Checking commands, note that the main function of this file is called create_root_design.