Debug PL Kernels Using the Vivado Logic Simulator - 2023.2 English

This section walks you through debugging PL kernels in the Vivado logic simulator.

1. In the Vitis IDE, launch the hardware emulation using Vitis -> Start/Stop Emulator.

2. Enable the Show Waveform option, and select Start.

3. This invokes the Vivado XSIM in standalone mode. Parallelly, you can observe the messages in the Vitis IDE Emulation Console.

4. Hit the Run button in the Vivado XSIM GUI taskbar, and observe the Linux bootup in the Vitis IDE Emulation Console.

5. Once the boot completes in the Vitis IDE, run the application using Run Configurations -> Launch HW Emulator on the system project.

6. Observe the data coming up in the XSIM and parallelly, the Emulation Console messages gets updated in Vitis IDE GUI.

7. After processing all the data, you can see the following messages in the Vivado XSIM Tcl Console:

   Info: (I804) /IEEE_Std_1666/deprecated: the notify() function is deprecated use sc_event::notify()
   // Interrupt Monitor : interrupt for ap_done detected @ "117153000"
   // Interrupt Monitor : interrupt for ap_ready detected @ "117153000"
   // Interrupt Monitor : interrupt for ap_done detected @ "118292000"
   // Interrupt Monitor : interrupt for ap_ready detected @ "118292000"
   // Interrupt Monitor : interrupt for ap_done detected @ "118478000"
   // Interrupt Monitor : interrupt for ap_ready detected @ "118478000"
   $stop called at time : 157304 ns
   run: Time (s): cpu = 00:00:36 ; elapsed = 00:03:57 . Memory (MB): peak = 13910.660 ; gain = 135.137 ; free physical = 23585 ; free virtual = 54027
   

   You can also notice the following messages in the Vitis IDE Emulation Console.

   XAIEFAL: INFO: Resource group Avail is created.
   XAIEFAL: INFO: Resource group Static is created.
   XAIEFAL: INFO: Resource group Generic is created.
   Input memory virtual addr 0x0xffff7fb56000x
   Output memory virtual addr 0x0xffff7fb55000x
   Output memory virtual addr 0x0xffff7fb54000x
   run mm2s
   run s2mm
   graph run
   graph end
   After MM2S wait
   After S2MM_1 wait
   After S2MM_2 wait
   TEST PASSED
   

8. Now observe the waveform in the Vivado XSIM GUI. The system contains one mm2s compute unit and two s2mm compute units. You can notice them in the waveform viewer as follows:

   

9. You can form a group of signals by right-clicking anywhere in the Name column, and select New Group. Add all the MM2S and S2MM-related signals to this group by dragging them correspondingly.

10. Zoom into the waveform window to locate the transactions clearly.

11. The m_axi_gmem is the transaction level signal which indicates the Read transaction in mm2s and write transaction in s2mm.

12. The TDATA in mm2s shows the data that is being read into the AI Engine module. To correlate with the number of iterations (seven), you specified in the graph, observe the TREADY signal which goes high when the AI Engine module is ready to read and the TVALID signal goes high for all the Read transactions.

13. Similarly you can notice in s2mm_1 the TVALID is high indicating the valid data and the TLAST goes high at the end of every iteration, goes low during start of next iteration.

This way you should be able to identify whether a data is being sent/received, to/from the AI Engine module correctly or not.