Design Overview - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

This tutorial is based on a basic design, as shown below. This design contains two AI Engine kernels with an intermediate kernel in the PL. The overall system is fed and flushed from kernels that are also in the PL.

Diagram of the design

In a standard simulation scheme, you would have to perform several steps:

  • In x86simulator and aiesimulator, you would have to replace mm2s and the output of polar_clip with text test vectors and verify that the input of polar_cip and s2mm is as intended.

  • In hw_emu, you would have to build the three PL kernels mm2s, polar_clip, and s2mm either from RTL code or HLS, link them with Vitis compiler to create the XCLBIN file, create a complete host application that also verifies the output of the system, and then simulate using hw_emu.

This tutorial shows you how to write Python scripts and C++ traffic generators to replace these text files that you would have to create offline. It also allows you to simulate the design in various different ways:

  • In x86simulator, aiesimulator, and hw_emu

  • With text files as test vectors

  • With external traffic generators in Python or C++

A standard simulation with text files would be represented as shown below: