Estimating Power Using the Power Design Manager - 2023.2 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2023-11-29
Version
2023.2 English

The Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to the largest Versal and AMD Kria™ SOM products. It is the preferred power estimation tool for the Versal product family. More information can be found on the Power Design Manager (PDM) product page and in the Power Design Manager User Guide (UG1556).

The PDM has three modes to estimate power:

  • Manual Estimation Flow: All device and design parameters including device part, design resources (AI Engine, PL and AI Engine), clocks, toggle rate, etc. are input manually into the GUI.

  • Import Compilation Flow: The file generated from XPE or Vivado Report Power is imported into the PDM after compiling the design.

  • Import Simulation Flow: The file generated from XPE or Vivado Report Power is imported into the PDM after simulating the design.

This example uses the Import Compilation Flow mode to perform a Vectorless Power Analysis as defined in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907). This estimate is refined by running a simulation of the AI Engine portion of the design and updating the initial estimate.