By default, the python script generates
aie_wrapper_ext_tb_proj.tcl along with the wrapper Verilog file as mentioned in above section.
There are two ways to proceed based on the existence of the Vivado project. This tutorial can be run using
aie_wrapper_ext_tb_proj.tcl if there is no available project already created using Vivado. If you have your Vivado project, use the IP flow i.e.,
If you have already created a Vivado project, this Tcl script can be used for generating required sim_ipc_axis IPs. From within the existing Vivado project, inside the Tcl console source
aie_wrapper_ext_tb_ip.tcl. In the Vivado Tcl console, run the following command:
You need to ensure that project directory and
aie_wrapper_ext_tb_ip.tcl directory are the same. If
aie_wrapper_ext_tb_ip.tcl is in another directory, provide appropriate path while sourcing it.
This tcl script is responsible for generating sim_ipc_axis IPs in Vivado project.
After sourcing the tcl file, you will see hierarchy created in sim_1 fileset under Simulation_sources.
You can add the required files and directories for your project as mentioned in the following figure: