After coming up with 400 tile AI Engine design, the next step is the come up with the way to move data from DDR send it to the AI Engine. We do this by using the the Vitis™ core development kit, to create kernel code in C++ meant to be accelerated on the FPGA. The kernel code is compiled by the Vitis Compiler (
v++ -c) into kernel objects (XO). The following is a table describing each HLS PL kernel.
||Dual-channel data-mover that moves data from DDR to AXI4-Stream.||411 MHz|
||Packet switching kernel that packetizes AXI4-Stream data by generating a header packet and appropriately asserting
||Packet switching kernel that evaluates packet headers from incoming streams and reroutes data to one of 4 AXI4-Streams||499.5 MHz|
||Quad-channel data-mover that moves data from AXI4-Stream to DDR.||411 MHz|
Using Vivado timing closure techniques, you can increase the FMax if needed. To showcase the example, integrate using the 300 MHz clock. There is also a 400 MHz timing-closed design in the beamforming tutorial.