Introduction - 2023.1 English

Vitis Tutorials: AI Engine Development

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2023.1 English

The AMD Versal™ adaptive SoC is a fully programmable, heterogeneous compute platform that combines the following components:

  • Scalar Engines (a processor subsystem (PS) that includes Arm® processors)

  • Adaptable Engines (programmable logic (PL) and memory)

  • Intelligent Engines (including both AI and DSP Engines)

This tutorial demonstrates the steps to upgrade a 32-branch digital down-conversion chain so that it is compliant with the latest tools and coding practice. Examples for the following changes with side-by-side view of the original and upgraded code are included in the tutorial.

  • Converting coding style from kernel functions to kernel C++ classes

  • Relocating global variables to kernel class data members

  • Handling state variables to enable x86sim

  • Migrating Windows (deprecated) to buffers for non-stream based kernel I/O

  • Replacing kernel intrinsics with equivalent AI Engine APIs

  • Updating older pragmas

  • Supporting x86 compilation and simulation

You can find the design description in the Digital Down-conversion Chain Implementation on AI Engine (XAPP1351). The codebase associated with the original design can be found in the Reference Design Files.