Memory Interface Requirements - 2023.2 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2023-11-29
Version
2023.2 English

Every platform must declare at least one memory interface with the AXI slave port (S_AXI_*). 28 S_AXI_NOC memory interfaces are declared. The Vitis linker step connects DDR4 memory to these ports.