If you built from scratch, you can open the block design in the AMD Vivado™ project to view the new hardware platform at build/rev0/hw/_x/link/vivado/vpl/prj/prj.xpr.
Notice the new XSA hardware platform built on top of the custom platform you built in Module 01 (Creating a Custom Platform). It still contains the original building blocks: CIPS, NoC, AI Engine, Clocking Wizard, Processor Reset Systems, ctrl_sm, and 16 AXI4-Lite SmartConnect interfaces. However, you will also notice that only six of these are being used, and ten of them remain unused.
Each AXI4-Lite SmartConnect interface can have up to 15 AXI4-Lite master interfaces. Four of the AXI4-Lite SmartConnect interfaces have 15 AXI4-Lite master interfaces instantiated, one of them has 14, and one of them has four. This is total of 78 AXI4-Lite master interfaces which are connected to the newly linked PL kernels (three dlbf_data, 24 dlbf_coeff, three ulbf_data, 12 ulbf_coeff, 24 dlbf_slave, and 12 ulbf_slave kernels). The AI Engine is also connected to all the PL kernels through their AXI4-Stream interfaces.