NoC Connections - 2023.2 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2023-11-29
Version
2023.2 English

Connect the NoC up to other parts of the design. First, the ddr4_dimm1 port created at the beginning of the dr.bd.tcl script is connected to the NoC CH0_DDR4_0 interface. This configures the NoC to have a single memory controller port.

Connect the AXI Debug Hub IP to the master interface of the NoC ( M00_AXI), then connect the AI Engine to the second master interface of the NoC (M01_AXI). Set the AI Engine’s s00_axi_aclk to the NoC’s aclk9.

NoC Interface Category NoC Clock Connection Interface
M00_AXI PL aclk5 axi_dbg_hub_0/S_AXI
M01_AXI AI Engine aclk9 ai_engine_0/S00_AXI
S00_AXI PS CCI aclk0 ps_cips/FPD_CCI_NOC_0
S01_AXI PS CCI aclk1 ps_cips/FPD_CCI_NOC_1
S02_AXI PS CCI aclk2 ps_cips/FPD_CCI_NOC_2
S03_AXI PS CCI aclk3 ps_cips/FPD_CCI_NOC_3
S04_AXI PS PMC None ps_cips/PMC_NOC_AXI_0
S05_AXI PS NCI aclk6 ps_cips/FPD_AXI_NOC_0
S06_AXI PS NCI aclk8 ps_cips/FPD_AXI_NOC_1
S07_AXI PS RPU aclk7 ps_cips/FPD_LPD_AXI_0