PL Slave Kernels - 2023.2 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2023-11-29
Version
2023.2 English

The PL slave kernels are the dlbf_slave and the ulbf_slave kernels. These kernels store the output data generated from the AI Engine application. Open the AMD Vivado™ projects for the PL kernels and review their source code.

PL Slave Kernel Block Diagram

  • AXI BRAM Controller: The AXI BRAM Controller writes the control signals to the CSR module and reads the status signals from the CSR module at 100MHz.

  • CSR Module: The CSR module is a register interface that the AXI BRAM Controller accesses to access the Slave RAM. Below is the control and status register map for one data master module.

Control and Status Register Address Map

Register Space Offset Bits and Name R/W? Description
0x0 [31:0] ID R 32-bit ID Register.
0x4 [0] RESET W 1:assert, 0:de-assert. Also assigned to the slave_rst_bram input in CSR module.
0xC [11:0] NITER W Sets the number of iterations of the data to receive. The number of iterations is the number of data chunks AI Engine produces and sends to the PL Slave kernels. If this set to 0, data is transmitted from AI Engine forever. Also assigned to the niter_bram input in the CSR module.
0x20 [0] SLAVE_DONE R When this status register is 1'b, the RAM slave is done receiving data to AI Engine. Also assigned to the rxdone_bram input in the CSR module.
  • CDC Module: The control and status signals sent to the CSR module sync up with the slave RAM module through a clock domain crossing (CDC) module. It converts the 100 MHz control and status signals from CIPS to 400 MHz signals. The slave RAM module operate at 400 MHz. It also works the other way as well (converting 400 MHz signals from the slave RAM modules to 100 MHz signals to send to the CIPS).

  • Data Slave RAM Module: Contains the URAM instance that stores the output data produced by the AI Engine. There is one slave RAM module in the dlbf_slave and ulbf_slave PL kernels.