Phase 2 contains the following stages:
aie2: As in the previous phase, this stage builds an AI Engine application, but in this case, it uses the new platform constraints.
host: Compile the PS application.
package2: Create the PDI to load onto the device (
run_emu: Launch the simulation and verifies that the output is still correct.
The new platform is named
Phase1_container. It has been created by the
vitis --link stage during Phase1. The
.xsa file contains all the constraints corresponding to the interface and is located in the directory
# New platform
PFM := Phase1_container
# Phase 1 output
XCLBIN := ../Phase1/$(PFM).xclbin
XSA := ../Phase1/$(PFM).xsa
The first stage,
make aie2, consists of generating the AI Engine application graph using the previously created
.xsa file. The kernel itself has not changed but a kernel location constraint has been added to the graph so that you can see a big difference in the kernel placement. Check this new placement using Vitis Analyzer on the compile summary.
The second stage,
make host, is straightforward and you can see that the first object file that is created is
aie_control_xrt.o. It is built from the CPP file that has been generated by the second stage.
The third stage,
make package2, has various outputs. Among them is a file named
launch_hw_emu.sh, which is used to run the hardware emulation in the last stage.
The fourth and final stage,
make run_emu, starts the hardware emulation that also verifies the correctness of the output.