Platform Details - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

The base platform contains the control interface and processing system (CIPS), NoC,and the interfaces among them. The Vitis compiler linker step builds on top of the base platform by adding the PL kernels. To add the various functions in a system-level design, PL kernels are added to the base platform depending on the application (that is, the PL kernels present in each design might vary). In the design, the components are added by the Vitis compiler -l step

(see make xsa) and include the following:

  • gemm_large_ocm DSP kernel (gemm_large_ocm.xo)

  • Connections interfaces are defined in the system configuration file

To see a schematic view of the design with the extended platform as shown in the following figure, open the following in Vivado:

build/gemm_GEMM_SIZExGEMM_SIZExGEMM_SIZE/[hw|hw_emu]/_x/link/vivado/vpl/prj/prj.xpr