Port Instantiation - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

The first thing the create_root_design function does is to create two block design interface ports called SYS_CLK1_IN_0 and ddr4_dimm1 for the system clock and DDR memory ports.