Version: Vitis 2023.2
Introduction
AI Engine application development can start early in the system development stage. The AI Engine development team and the hardware development team slowly converge on an interface between the Adaptable Engine and the AI Engine array. At some point, this interface is fixed and should not be changed. This tutorial shows you how to modify an AI Engine application after the platform has been frozen while avoiding a complete AMD Vivado™ tool run, which might take long if timing closure requires specific attention.
There are two ways to perform this operation:
Recompile the AI Engine application right after the link stage, using specific constraints to set the interface ports.
Use the output
.xsafile as a platform, which embeds these constraints.
In the first case, you have to extract the constraints from the files generated by the AI Engine compiler and use them as input constraints when you run it for the second time.
In the second case, you use the .xsa file generated during the link stage as the target platform, which contains the constraints already on the AI Engine array interface specification. This tutorial explains the complete flow for these two cases.
This tutorial details all the steps to perform hardware emulation (hw_emu), but it also supports the hardware implementation flow by changing the compilation target.
IMPORTANT: Before beginning the tutorial, make sure that you have installed the Vitis 2023.2 software. The AMD Vitis™ release includes all the embedded base platforms including the VCK190 base platform that is used in this tutorial. In addition, ensure that you have downloaded the Common Images for Embedded Vitis Platforms from this link https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms/2023-1.html. The ‘common image’ package contains a prebuilt Linux kernel and root file system that can be used with the Versal board for embedded design development using Vitis. Before starting this tutorial, run the following steps:
Go to the directory where you have unzipped the Versal Common Image package.
In a Bash shell, run the
/Common Images Dir/xilinx-versal-common-v2023.2/environment-setup-cortexa72-cortexa53-xilinx-linuxscript. This script sets up theSDKTARGETSYSROOTandCXXvariables. If the script is not present, run the/Common Images Dir/xilinx-versal-common-v2023.2/sdk.sh.Set up your
ROOTFS, andIMAGEto point to therootfs.ext4andImagefiles located in the/Common Images Dir/xilinx-versal-common-v2023.2directory.Set up your
PLATFORM_REPO_PATHSenvironment variable to$XILINX_VITIS/lin64/Vitis/2023.2/base_platforms/.
This tutorial targets the VCK190 production board for 2023.2 version.
The sub-directory Files contains all the source files necessary for this tutorial.
AI Engine Application Post-Link Recompile
This tutorial contains the following labs:
Each lab is divided into the following phases:
Creating an AI Engine application using the VCK190 platform with all necessary PL kernels added, and linking the complete system.
Creating a new AI Engine application with interface location constraints (Lab 1) or with the previously created fixed platform (Labs 2), adding a PS application, and running hardware emulation.
Objectives
This tutorial shows you how to modify an AI Engine application after the platform has been frozen. It demonstrates a Vitis Makefile flow.
Completing this tutorial should give you the confidence to develop AI Engine designs based on a hardware/software platform, knowing that you can modify the AI Engine part and the processing system control application. The only limitation is that the hardware connection between the AI Engine array and the programmable logic (PL) must be kept fixed.
License
The MIT License (MIT)
Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: MIT
Support
GitHub issues will be used for tracking requests and bugs. For questions, go to support.xilinx.com.
Copyright © 2020–2023 Advanced Micro Devices, Inc
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