Post-Link Recompile of an AI Engine Application - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
Release Date
2022.2 English

Version: Vitis 2022.2


AI Engine application development can start early in the system development stage. Little by little, the AI Engine development team and the hardware development team converge to an interface between the Adaptable Engine and the AI Engine array. At some point, this interface is fixed and should not be changed. This tutorial shows you how to modify an AI Engine application after the platform has been frozen while avoiding a complete Vivado® tool run, which can take a long time if timing closure requires specific attention.

There are two ways to perform this operation:

  1. Recompile the AI Engine application right after the link stage, using specific constraints to set the interface ports.

  2. Use the output .xsa file as a platform which embeds these constraints.

In the first case, you have to extract the constraints from the files generated by the AI Engine compiler and use them as input constraints when you run it for the second time.

In the second case, you use the .xsa file generated during the link stage as the target platform which contains already the constraints on the AI Engine array interface specification. This tutorial explains the complete flow for these two cases.

This tutorial details all the steps to perform hardware emulation (hw_emu), but it supports also the hardware implementation flow by changing the compilation target.

IMPORTANT: First, set up the Vitis™ unified software platform and install the VCK190 base platform. Follow the instructions in the Vitis Software Platform Release Notes (v2022.2).

Before you begin this tutorial, run the following steps:

  1. Set up your platform by running the xilinx-versal-common-v2022.2/environment-setup-cortexa72-cortexa53-xilinx-linux script as provided in the platform download. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run xilinx-versal-common-v2022.2/

  2. Set up your ROOTFS to point to xilinx-versal-common-v2022.2/rootfs.ext4.

  3. Set up your IMAGE to point to xilinx-versal-common-v2022.2/Image.

  4. Set up your PLATFORM_REPO_PATHS environment variable based on where you downloaded the platform.

The sub-directory Files contains all the source files necessary for this tutorial.

AI Engine Application Post-Link Recompile

This tutorial contains the following labs:

  • Lab 1 is based on a direct recompile Makefile flow.

  • Lab 2 is based on a Vitis Makefile flow.

Each lab is divided into the following phases:

  1. Creating an AI Engine application using the VCK190 platform with all necessary PL kernels added, and linking the complete system.

  2. Creating a new AI Engine application with interface location constraints (Lab 1) or with the previously created fixed platform (Labs 2), adding a PS application, and running hardware emulation.


This tutorial shows you how to modify an AI Engine application after the platform has been frozen. It demonstrates a Vitis Makefile flow.

Completing this tutorial should give you confidence to develop AI Engine designs based on a hardware/software platform, knowing that you can modify the AI Engine part and the processing system control application. The only limitation is that the hardware connection between the AI Engine array and the programmable logic (PL) must be kept fixed.


GitHub issues will be used for tracking requests and bugs. For questions go to


Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.

You may obtain a copy of the License at

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

XD039 | © Copyright 2021–2022 Xilinx, Inc.