Section 2: How to integrate external RTL (Verilog/SV) based traffic generator with AIE. - 2022.2 English

Vitis Tutorials: AI Engine Development

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2022.2 English

In order to establish the connection between the RTL and the AIE kernel’s external PLIOs; the XTLM_IPC SystemC modules are required for the interface between an RTL and AIE kernel and these stubs are present inside external aie wrapper stub module which includes all the XTLM IPC modules and needs to be instantiated in the external testbench to establish the connection as mentioned in below figure. The axi_stream connections from the RTL kernel are made to the stub which transfers the data to AIE kernel and vice versa as seen in below figure: