Stage 1: Create and Simulate the Design - 2023.2 English

1. On the MATLAB GUI, select the Home Tab, and click Simulink.

   

2. Select Blank Model to create a new canvas on which to design the Decimation Chain.

   

   Perform the next two steps to enhance the User Experience. This allows you to have an instant access to the initialization file and to automatically call it when opening the design or when you update it.

3. Right-click in the canvas, and select Model Properties:

   • Click the Callbacks tab.

   • Click PreLoadFcn, and type CreateFilter; in the edit window on the right.

   • Click InitFcn, and type CreateFilter; in the edit window on the right.

   • Click Apply.

     

4. Click on the canvas, and type subsys. Select the first Subsystem displayed in the list (Subsystem, Simulink/Ports & Subsystem).

   

   • Double-click the new block, and remove all blocks inside (CTRL-A and Del).

   • Go back to the top level by clicking on the Up-arrow.

   

   • Right-click the Subsystem, and select Properties.

   • Click the Callbacks tab.

   • Select OpenFcn in the Callback function list.

   • Type open('CreateFilter.m'); in the edit window on the right.

   • Click Apply and OK.

   Now when you double-click this block, you will open the initialization matlab function (CreateFilter.m) in the MATLAB editor. Save the model CTRL+S, and assign the name VMC_DSPLib.

5. Click the Library Browser icon.

   

   In the list of libraries, you will find the AMD Toolbox. This contains four sub-libraries:

   • AI Engine

   • HDL

   • HLS

   • Utilities

   Click the AI Engine section. This reveals seven subsections:

   • DSP

   • Interfaces

   • Signal Routing

   • Sinks

   • Sources

   • Tools

   • User-Defined functions

6. Click the DSP sub-section. There are two sub-menu entries:

   • Buffer IO: which contains filter implementations using frame-based input and output.

   • Stream IO : which contains filter implementations using streaming input and output.

7. Click the Buffer IO sub-section and place the FIR Halfband Decimator block in the canvas as shown in the following figure.

   

8. Double-click the FIR Halfband Decimator block to open the GUI. Populate the GUI with the following parameters :

   • Input/output data type: cint16

   • Filter coefficients data type: int16

   • Filter coefficients: hb1_aie

   • Input Window size (Number of samples): 2048

   • Scale output down by 2: Shift1

   • Rounding mode: Floor

   Leave all other settings at their default values. Click Apply and OK.

   

   Now create a data source to feed this filter.

9. Create the following two blocks by clicking the canvas and typing the beginning of the name of the block. Then enter the given parameters:

Name to Type	Block Name to Select	Parameters
random	Random Source	Source Type: Uniform Minimum: -30000 Maximum: 30000 Sample time: 1 Samples per frame: 2048 Complexity: complex
cast	Cast	Output data type: int16

1. Cascade the three blocks: Random Source, Cast, AIE FIR Filter.

2. The file ReferenceChain.slx contains the decimation chain using Simulink blocks. Open ReferenceChain.slx. Copy the block HB1 over to your design.

3. Copy the small set of blocks (To Fixed Size, Subtract, Scope, Vitis Model Composer Hub) to create the following design:

   

4. Ensure that the parameter Output Size of the block To Fixed Size is set to 1024.

5. Set the Stop Time to 5000, and run the design. The FIR filter is compiled and the design is run. The scope should show a completely null difference.

6. To gain more information about the signals traveling through the wires, update the following display parameters:

   • Right-click the canvas, and select Other Displays –> Signals and Ports –> Signal Dimensions.

   • Right-click the canvas, and select Other Displays –> Signals and Ports –> Port Data Types.

   • Right-click the canvas, and select Sample Time Display –> all.

     After updating the design with CTRL-D, the display should look as follows:

     

     Notice that before the implementing the Decimation Filter the vector length was 2048, but after implementation this was reduced to 1024.

7. Update the design with the other three filters using the following parameters:

  | Parameter |HB1 |    HB2 | HB3   | Channel Filter |
  | :--- | :--- |  :--- | :--- | :--- |
  | Filter Block    | FIR Halfband Decimator | FIR Halfband Decimator   | FIR Halfband Decimator    | FIR Symmetric Filter |
  | Input Output data type  | cint16    | cint16    | cint16    | cint16 |
  | Filter Coefficients Data Type   | int16 | int16 | int16 | int16 |
  | Filter Coefficients | hb1_aie   | hb2_aie   | hb3_aie   | cfi_aie |
  | Filter Length   | N/A | N/A | N/A | length(cfi) |
  | Input window size (Number of samples)   | 2048  | 1024  | 512   | 256 |
  | Scale output down by 2^ | Shift1    | Shift2    | Shift3    | ShiftCF |
  | Rounding mode   floor   | floor | floor | floor | floor |

1. Update the Output Size parameter of the To Fixed Size block to 256. The design should display like as follows:

   

2. Run the design. The added filters are compiled, and the design is run through the 5000 samples. The difference between the output should still be 0.