Stage 4: Increasing PLIO bitwidth and re-generate - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

Solving this problem is fairly easy. Navigate inside the FIRchain sub-system. Get the PLIO block from Xilinx Toolbox / AI Engine / Interface or just type plio in the canvas. Double-click on the new block and specify:

  • PLIO width (bits): 128

  • Check Specify PLIO frequency

  • PLIO frequency (MHz) : 250

Click OK. Place the block just after the input port, and a copy of this block just before the output port:

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Re-open the Vitis Model Composer Hub and click Generate to re-compile and re-simulate the design.

After the AI Engine simulation, the estimated throughput is 177 MSPS. This is computed from the following timestamped (green) output data:

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Three frames are received but only two interframe idle time are taken into account. A more precise estimate woul be to count the 512 output samples in between the 2 red vertical line. This gives almost 125 MSPS which is 1/8th of the input sample rate (1 GSPS). This means that the design can support for sure the 800 MSPS that were specified in the design.