Solving this problem is fairly easy. Navigate inside the FIRchain sub-system. Get the PLIO block from AMD Toolbox / AI Engine / Interface, or just type plio in the canvas. Double-click on the new block and specify:
PLIO width (bits): 128
Check Specify PLIO frequency
PLIO frequency (MHz) : 250
Click OK. Place the block just after the input port, and a copy of this block just before the output port:
Re-open the Model Composer Hub block, and click Generate to re-compile and re-simulate the design.
After the AI Engine simulation, the estimated throughput is 126 MSPS. This is computed from the following timestamped (green) output data, calculated for two full frame periods:
This gives around 125 MSPS which is 1/8th of the input sample rate (1 GSPS). This means that the design meets specification.