In this design, you will use three kernels called: MM2S, S2MM, and Polar_Clip, to connect to the PLIO. The MM2S and S2MM are AXI memory-mapped to AXI4-Stream HLS designs to handle mapping from DDR and streaming the data to the AI Engine. The Polar_Clip is a free running kernel that only contains two AXI4-Stream interfaces (input and output) that will receive data from the AI Engine, process the data, and send it back to the AI Engine. Clocking of these PLIO kernels is separate from the ADF Graph, and these are specified when compiling the kernel, and when linking the design together.
Run the following commands.
v++ -c --mode hls --platform $PLATFORM_REPO_PATHS/xilinx_vck190_base_202310_1/xilinx_vck190_base_202310_1.xpfm
--freqhz=150000000 --config pl_kernels/mm2s.cfg \
v++ -c --mode hls --platform $PLATFORM_REPO_PATHS/xilinx_vck190_base_202310_1/xilinx_vck190_base_202310_1.xpfm
--freqhz=150000000 --config pl_kernels/s2mm.cfg \
v++ -c --mode hls --platform $PLATFORM_REPO_PATHS/xilinx_vck190_base_202310_1/xilinx_vck190_base_202310_1.xpfm
--freqhz=200000000 --config ./pl_kernels/polar_clip.cfg \
A brief explanation of the v++ options:
| Flag/Switch | Description |
|---|---|
-c |
Tells v++ to run the compiler. |
--mode |
Tells v++ to run the HLS mode for the PL compilation. |
--platform |
(required) The platform to be compiled towards. |
--freqhz |
Tells the Vitis compiler to use a specific clock defined by a nine digit number. Specifying this will help with the compiler make optimizations based on kernel timing. |
--config |
to specify the kernel config file that contains settings for synthesis like top function, kernel name etc. |
For additional information, see Vitis Compiler Command.
After completion, you will have the mm2s.xo, s2mm.xo, and polar_clip.xo files ready to be used by v++. The host application will communicate with these kernels to read/write data into memory.