Step 2: Linking for Hardware Emulation - 2023.1 English

In a standard simulation, the various XO files (mm2s, polar_clip, and s2mm) would be created and linked to the AI Engine array, leaving no room for the external traffic generators. A configuration file for such a simulation can be seen in system.cfg:

[connectivity]
nk=mm2s:1:mm2s
nk=s2mm:1:s2mm
nk=polar_clip:1:polar_clip

sc=mm2s.s:ai_engine_0.DataIn1
sc=ai_engine_0.clip_in:polar_clip.sin
sc=polar_clip.sout:ai_engine_0.clip_out
sc=ai_engine_0.DataOut1:s2mm.s

To work with external traffic generators in hardware emulation, introduce hooks in the PL. For that purpose, AMD provides a complete set of XO files with various bitwidths in $XILINX_VITIS/data/emulation/XO/:

• sim_ipc_axis_master_NNN.xo with NNN in 8, 16, 32, 64, 128, 256, 512

• sim_ipc_axis_slave_NNN.xo with NNN in 8, 16, 32, 64, 128, 256, 512

In this tutorial, there are 32-bit interfaces. Copy the files sim_ipc_axis_master_32.xo and sim_ipc_axis_slave_32.xo into the pl_kernels directory. The configuration file is the one in system_etg.cfg:

[connectivity]
nk=sim_ipc_axis_master_32:2:mm2s.polar_clip_out
nk=sim_ipc_axis_slave_32:2:s2mm.polar_clip_in

sc=mm2s.M00_AXIS:ai_engine_0.DataIn1
sc=ai_engine_0.clip_in:polar_clip_in.S00_AXIS
sc=polar_clip_out.M00_AXIS:ai_engine_0.clip_out
sc=ai_engine_0.DataOut1:s2mm.S00_AXIS