Step-3: Linking for Hardware Emulation - 2023.2 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2023-11-29
Version
2023.2 English

In a standard simulation, the various XO files of data movers and PL processing streaming kernel (mm2s, polar_clip, s2mm) would be created and linked to the AI Engine array, leaving no room for the external traffic generators. A configuration file for such a simulation can be seen in system.cfg:

[connectivity]
nk=mm2s:1:mm2s
nk=s2mm:1:s2mm
nk=polar_clip:1:polar_clip

sc=mm2s.s:ai_engine_0.in_interpolator
sc=ai_engine_0.clip_in:polar_clip.in_sample
sc=polar_clip.out_sample:ai_engine_0.in_classifier
sc=ai_engine_0.out_classifier:s2mm.s

To work with external traffic generators in hardware emulation, introduce hooks in the PL and replace the mm2s/s2mm XOs with the the sim IPC master and slave hooks. For that purpose, AMD provides a complete set of pre built XO files with various bit widths located inside $XILINX_VITIS/data/emulation/XO/:

sim_ipc_axis_master_NNN.xo with NNN in 8, 16, 32, 64, 128, 256, 512 bits
sim_ipc_axis_slave_NNN.xo with NNN in 8, 16, 32, 64, 128, 256, 512 bits

In this tutorial, there are 32-bit interfaces.

The configuration file is the one in system_etg.cfg. Note that the XO instance names “in_interpolator” for sim_ipc_axis_master_32 and “out_classifier” for sim_ipc_axis_slave_32 should match with that of the external ports in the external traffic generator code that becomes a key which will be used by the external process to refer to a particular stream port.

[connectivity]
nk=sim_ipc_axis_master_32:1:in_interpolator
nk=sim_ipc_axis_slave_32:1:out_classifier
nk=polar_clip:1:polar_clip
sc=in_interpolator.M00_AXIS:ai_engine_0.in_interpolator
sc=ai_engine_0.out_interpolator:polar_clip.in_sample
sc=polar_clip.out_sample:ai_engine_0.in_classifier
sc=ai_engine_0.out_classifier:out_classifier.S00_AXIS