Step 3 - v++ linker – Building the System - 2023.2 English

Vitis Tutorials: AI Engine

Document ID
XD100
Release Date
2023-11-29
Version
2023.2 English

Now that you have a compiled graph (libadf.a), the PLIO kernels (mm2s.xo, s2mm.xo, and polar_clip.xo), you can link everything up for the VCK190 platform.

A few things to remember in this step:

  1. For PLIO kernels, you need to specify their connectivity for the system.

  2. Specify the clocking per PL kernel.

  3. You need to determine the TARGET: hw or hw_emu.

To link kernels up to the platform and AI Engine, you will need to look at the system.cfg file. For this design, the config file looks like this:

[connectivity]
nk=mm2s:1:mm2s
nk=s2mm:1:s2mm
nk=polar_clip:1:polar_clip
stream_connect=mm2s.s:ai_engine_0.DataIn1
stream_connect=ai_engine_0.clip_in:polar_clip.in_sample
stream_connect=polar_clip.out_sample:ai_engine_0.clip_out
stream_connect=ai_engine_0.DataOut1:s2mm.s

Here you might notice some connectivity and clocking options.

  • nk: This defines your PL kernels as such: <kernel>:<count>:<naming>. For this design, you only have one of each s2mm, mm2s, and polar_clip kernels.

  • stream_connect: This tells v++ how to hook up the previous two kernels to the AI Engine instance. Remember, AI Engine only handles stream interfaces.

With the changes made, you can now run the following command:

    v++ --link --target hw --platform $PLATFORM_REPO_PATHS/        xilinx_vck190_base_202210_1/xilinx_vck190_base_202210_1.xpfm 
    pl_kernels/s2mm.xo pl_kernels/mm2s.xo pl_kernels/polar_clip.xo ./aie/libadf.a --freqhz=200000000:mm2s.ap_clk --freqhz=200000000:s2mm.ap_clk 
    --config system.cfg --save-temps -o tutorial1.xsa

| Flag/Switch | Description | | — | —| | --link | Tells v++ that it will be linking a design, so only the *.xo and libadf.a files are valid inputs. | | --target | Tells v++ how far of a build it should go, hardware (which will build down to a bitstream) or hardware emulation (which will build the emulation models).| | --platform | Same from the previous two steps.| | --freqhz | Tells the Vitis compiler to use a specific clock defined by a nine digit number. Specifying this will help with the compiler make optimizations based on kernel timing.| | --config | to specify the kernel config file that contains settings for synthesis like top function, kernel name etc.|

Once the linking is done, you can view clock report generated by v++ –link after pre-synthesis: automation_summary_pre_synthesis.txt

IPI Diagram

**IMPORTANT: Do not change anything in this view. This is only for demonstration purposes.**
  • As we can see that AIE compile frequency= 200 MHz (same as given in command in step 1)

  • To compile, PL kernel frequency for mm2s = 150 MHz (same as given in command in step 2.1)

  • To compile, PL kernel frequency for s2mm = 150 MHz (same as given in command in step 2.2)

  • To compile, PL kernel frequency for Polar_clip = 200 MHz (same as given in command in step 2.3)

To check the platform frequency, give command at terminal: platforminfo /proj/xbuilds/2023.2_daily_latest/internal_platforms/xilinx_vck190_base_202320_1/xilinx_vck190_base_202320_1.xpfm

Clock frequency used by Vitis for linking are derived in following way:

* Clock frequency used in linking for mm2s = 200 MHz (CLI)

* Clock frequency used in linking for s2mm = 200 MHz (CLI)

* Clock frequency used in linking for polar_clip = 100 MHz (config file)

Since these clock frequencies are not matching with the platform clock frequency, so vitis picked the clock frequency from the platform which is coming under the default tolerance (+/- 10%). If link frequency is outside the limit of tolerance new MMCM would be instantiated by Vitis to generate the clock frequency used in linking.

So, for linking, the clock frequency used by Vitis in a following way:

For mm2s:

Frequency given during linking = 200 MHz

Frequency used by Vitis = 208.33 MHz (platform clock coming under the default tolerance of clock frequency given in link command)

For s2mm:

Frequency given during linking = 200 MHz

Frequency used by Vitis = 208.33 MHz (platform clock coming under the default tolerance of clock frequency given in link command)

For polar_clip:

Frequency given during linking = 100 MHz

Frequency used by Vitis = 104.17 MHz (platform clock coming under the default tolerance of clock frequency given in link command)

NOTE: Any change to the system.cfg file can also be done on the command line. Make sure to familiarize yourself with the Vitis compiler options by referring to the documentation here.