Step 4.9. Setup design’s signals to be debugged - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

Click on + to configure the desired signals and their values during run time.

Example below selects TVALID signal from mm2s_v4_1_s0 and vitis_design_s2mm_v4_1_0_so interfaces that capture valid transfers are driven from master. Set value to B (both transition so transitions of valid data signals can be captured.