There are many different ways to close timing. This section details how timing closure been approached in the beamforming design.
First, find the problematic paths that resulted in the negative slack. The longest paths in the design are between the PL kernels and AI Engine, which cannot operate at 400 MHz clock frequency without negative slack.
The first thing to do is try to break up these paths and reduce the amount of time it takes to get from the PL kernel to the AI Engine. This was done by introducing two AXI register slice IPs in the paths to pipeline the data flow.
In addition to adding the AXI register slices, we also explored timing closure strategies that could be applied during each stage of implementation: placement, routing, and physical optimization. The full list of strategies available for each stage is documented in Vivado Design Suite User Guide Implementation Chapter 2: Implementing the Design (UG904).