Section 1: Compile AI Engine code using the AI Engine compiler for x86simulator, viewing compilation results in Vitis Analyzer.
Section 2: Simulate the AI Engine graph using the x86simulator.
Section 3: Run software emulation using QEMU and x86 process.
Section 4: Compile AI Engine code for aiesimulator, viewing compilation results in Vitis Analyzer.
Section 5: Simulate the AI Engine graph using the aiesimulator and viewing trace and profile results in Vitis Analyzer.
Section 6: Run the hardware emulation, and view run summary in Vitis Analyzer.
Section 7: Run on hardware.
The design that will be used is shown in the following figure.
| Kernel | Type | Comment |
|---|---|---|
| MM2S | HLS | Memory Map to Stream HLS kernel to feed input data from DDR to AI Engine interpolator kernel via the PL DMA. |
| Interpolator | AI Engine | Half-band 2x up-sampling FIR filter with 16 coefficients. Its input and output are cint16 window interfaces and the input interface has a 16 sample margin. |
| Polar_clip | AI Engine | Determines the magnitude of the complex input vector and clips the output magnitude if it is greater than a threshold. The polar_clip has a single input stream of complex 16-bit samples, and a single output stream whose underlying samples are also complex 16-bit elements. |
| Classifier | AI Engine | This kernel determines the quadrant of the complex input vector and outputs a single real value depending which quadrant. The input interface is a cint16 stream and the output is a int32 window. |
| S2MM | HLS | Stream to Memory Map HLS kernel to feed output result data from AI Engine classifier kernel to DDR via the PL DMA. |