Versal System Design Clocking - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID: XD100
Release Date: 2022-12-01
Version: 2022.2 English

Vitis Tutorials: AI Engine Development
Environment Settings
Feature Tutorials
Design Tutorials
Feature Tutorials
AI Engine A-to-Z Flow for Linux
AI Engine GMIO Performance Profile
Prerequisites
Setting up the environment
Re-compiling ADF graph
Re-compiling Programmable Logic (PL) kernels targeting the custom platform
Hardware Emulation
Targeting Hardware
Support
License
A to Z Bare-metal Flow
Custom Base Platform Creation
Platforms
Step 1. Build Versal Extensible Embedded Platform Example Design in Vivado
Step 2. Build the Platform in the Vitis Software Platform
AIE Application Creation
Step 1. Create a new AI Engine Application Project
Step 2. Build the Project and Run Through Emulation-AIE
PL Application Creation
Step 1. Modify the Graph for Use in Hardware Build
Step 2. Add PL Kernels
Step 3. Configure Hardware Linking Project
Step 4. Build the System
PS Application Creation
Step 1. Create a New Platform in the Bare-metal Domain
Step 2. Build the Baremetal AI Engine Control Application
Step 3. Build the Full System
Step 4. Run the System in Hardware Emulation
Step 5. Build the System targeting the Hardware
Step 6. Run the System in Hardware
Summary
RPU Version (Optional)
Base Platform Changes
Rebuild Simple Application System Project
Update Fixed Platform
PS Application Project Changes
Using GMIO with AIE
AI Engine GMIO Performance Profile
AI Engine GMIO Performance Profile
AI Engine GMIO Performance Profile
Design Introduction
Performance Profiling Methods
In this example, some methods for profiling the design are introduced. The code to be profiled is in aie/graph.cpp:
Performance Profiling Methods
Conclusion
AI Engine GMIO Programming Model
Step 1 - Synchronous GMIO Transfer
Run AI Engine compiler and AI Engine simulator
Step 2 - Asynchronous GMIO Transfer for Input and Synchronous GMIO Transfer for Output
Run AI Engine compiler and AI Engine simulator
Step 3 - Asynchronous GMIO Transfer and Hardware Flow
Run AI Engine simulator and hardware flow
Conclusion
Runtime Parameter Reconfiguration
Step 1: Sync Scalar
Review Graph Programming Code
Review RTP Update Code
Run AI Engine Compiler and AI Engine Simulator
Build for Hardware Emulation and Hardware Flow
Deploy for Hardware Emulation and Hardware Flow
Conclusion
Support
License
Step 2: Sync Scalar
Review RTP Update Code
Run AI Engine Compiler and AI Engine Simulator
Run Hardware Cosimulation and Hardware Flow
Conclusion
Support
License
Step 3: Sync Scalar
Review Graph and RTP Code
Run the AI Engine Compiler and AI Engine Simulator
Run Hardware Emulation and Hardware Flow
Conclusion
Support
License
Step 4: Sync Scalar
Review Graph and RTP Code
Run AI Engine Compiler and AI Engine Simulator
Run Hardware Cosimulation and Hardware Flow
Conclusion
Support
License
Step 5: Sync Scalar
Review Graph and RTP Code
Run AI Engine Compiler and AI Engine Simulator
Run Hardware Cosimulation and Hardware Flow
Conclusion
Support
License
Packet Switching
Packet Stream Based AI Engine Kernels
Packet Stream Interfaces and Operations
Construct Graph for Packet Stream Kernels
Run the AI Engine Simulator, HW Emulation, and HW Flows
Conclusion
Support
License
Window Based AI Engine Kernels
Construct Graph with Packet Switching Capability
Packet Format
Prepare Data and Run AI Engine Simulator
Example PL Kernels for Packet Switching
Example PS code for Packet Switching
Run Hardware Emulation and Hardware flows
Conclusion
Window Based AI Engine Kernels with Mixed Data Types
Prepare Data for AI Engine Simulator
PS Application and HW Emulation Flows
Conclusion
Support
License
Versal Integration for Hardware Emulation and Hardware
Introduction
Objectives
Tutorial Overview
Section 1: Compile AI Engine code using the AI Engine compiler for x86simulator, viewing compilation results in Vitis Analyzer.
Compiling an AI Engine ADF Graph for V++ Flow
Vitis Analyzer Compile Summary
Section-2: Simulate the AI Engine graph using the x86simulator
Vitis Analyzer
Section 3: Compile and Run software emulation.
1. Compiling HLS Kernels Using v++
2. Use V++ to Link AI Engine, HLS Kernels with the Platform
3. Compile the A72 Host Application
4. Package the Design
5. Run Software Emulation
Run PS application as an ARM process (QEMU)
Run PS application on x86 process
Section 4: Compile AI Engine code for AIE Simulator, viewing compilation results in Vitis™ Analyzer
Compiling an AI Engine ADF Graph for V++ Flow
Vitis Analyzer Compile Summary
Section 5: Simulate the AI Engine graph using the aiesimulator and viewing trace, and profile results in Vitis Analyzer.
Vitis Analyzer
Summary
Profile
Graph
Array
Simulator Output
Section 6: Run the hardware emulation, and view run summary in Vitis Analyzer.
1. Compiling HLS Kernels Using v++
2. Use V++ to Link AI Engine, HLS Kernels with the Platform
3.Compile the A72 Host Application
4.Package the Design
5.Run Hardware Emulation
Section 7: Build and Run on Hardware
Summary
Support
License
Versal System Design Clocking
Introduction
Objectives
Step 1 - Building ADF Graph
Step 2 - Clocking the PL Kernels
Step 3 - v++ linker – Building the System
Step 4 - Compiling Host Code
Step 5 - Packaging Design and Running on Board
Challenge (Optional)
Build the design for Hardware Emulation
Summary
Using Floating-Point in the AI Engine
Introduction
AI Engine Architecture Details
Fixed-Point Pipeline
Floating-point Pipeline
Floating-point intrinsics
Start, offset
fpneg, fpabs, fpadd, fpsub
fpneg
fpabs
fpneg_abs
fpadd, fpsub
fpadd_abs, fpsub_abs
fpmul
fpabs_mul
fpneg_mul
fpneg_abs_mul
fpmac, fpmsc, fpmac_abs, fpmsc_abs
fpmul_conf, fpmac_conf
Floating-Point Examples
FIR Filter
Real Floating-Point Filter
Complex Floating-Point Filter
Matrix Multiply
License
DSP Library
Introduction
Part 1: Creating a Single Kernel Graph
Understanding the Source Files
Compile the application
Running the Design through Simulation
Using Vitis Analyzer to look at the Simulation Results
Part 2: Creating a Multi Kernel Graph
Changes to the Filter Graph from Part 1
Build AI Engine Emulation
Running the Design through Simulation
Using Vitis Analyzer to look at the Compilation and Simulation Results
Part 3: Optimizing Filter Performance
Changes to the Filter Graph from Part 1
Build AI Engine Emulation
Running the Design through Simulation
Using Vitis Analyzer to look at the Compilation and Simulation Results
Conclusion
License
Debug Walkthrough
Migrate Command-Line Based Projects to Vitis IDE
Step 1: Create project
Step 2: Import project source code
Step 3: Configure project
Step 3.1: Configure AI Engine sub-project
Step 3.2: Configure hardware link
Step 3.3: Configure hardware kernels
Step 3.4: Configure PS sub-project
Step 4: Configure system project in packaging options
Support
License
AI Engine Debug with X86simulator
1. Launch and Verify Software Emulation in Vitis IDE
Step 1.1 Select Software Emulation Configuration
Step 1.2 Build Configuration
Step 1.3 Build with x86 Emulator
Step 1.4 Run with x86 Emulator
Step 1.5 Console Displays Emulation Result
Step 1.6 Verify Run Result
2. printf Support
Step 2.1 Add printf() statement
Step 2.2 Compile the Project
Step 2.3 Run the Project
Step 2.4 Expected Result
3. Printf() with Vector Data Types
Step 3.1 Add printf() in source code
Step 3.2 Compile and Run x86simulator
Step 3.3 Expected Result
Step 3.4 Reverse Added printf() Statements
4. Vitis IDE Debugger Support
Step 4.1 Launch SW Emulator Debugger
Step 4.2 Debug during Run Time
Step 4.3 Inspect Array Values
5. x86simulator Configuration File
6. x86simulator Features
x86simulator Data Dump
Step 6.1.1 Enable Dump Feature
Step 6.1.2 Run x86simulator
x86simulator Deadlock Detection
Step 6.2.1 Enable Deadlock Detection Feature
Step 6.2.2 Setup Deadlock Condition
Step 6.2.3 Run x86simulator
Step 6.2.4 Converts Generated dot file to png file with dot Application
x86simulator Trace Report
Step 6.3.1 Enable Trace Feature
Step 6.3.2 Run x86simulator
Step 6.3.3 x86simulator Trace Events supported
Differences between trace and trace-print
x86simulator Memory Access Violation and Valgrind
Step 6.4.1 Setup Environmental Variables
Step 6.4.2 Enable Valgrind Feature
Step 6.4.3 Run x86simulator
Step 6.4.4 Error Message with an Unintialized Variable
Step 6.4.5 Expected Errors from valgrind
Step 6.4.6 Reverse Added Error
7. Command Line Projects Support
x86simulator Using GDB
Step 7.1.1 Download the project
Step 7.1.2 Prepare Makefiles and source code
Step 7.1.3 Build Project
Step 7.1.4 Enable GDB to Work with x86simulator
Step 7.1.5 GDB Commands
x86simulator Using GDB server
Step 7.2.1 Project preparation
Step 7.2.2 Enable GDB Server to Work with x86simulator
Step 7.2.3 Launch GDB Server
Step 7.2.4 Using GDB Commands
Limitations
Support
License
AI Engine Debug with Software Emulator
1. Prepare Software Emulation Project in Vitis IDE
Step 1.1 Select Software Emulation Configuration
Step 1.2 Build AI Engine domain project
Step 1.3 Import aie_control_xrt.cpp to PS domain
Step 1.4 Import host.cpp to PS domain
Step 1.5 Build system project
2. Run and Verify Software Emulation in Vitis IDE
Step 2.1 Configure Environment Variables
Step 2.2 Run with Software Emulator
Step 2.3 Verify Run Result
3. Launch Debugger to Debug Design
Step 3.1 Launch Software Emulation Debugger
Step 3.2 Debug with Software Emulator
4. Command line project build and run with software emulator
Step 4.1 Download the project
Step 4.2 Prepare Makefiles and source code
Step 4.3 Build project
Step 4.4 Run project
Step 4.5 Petalinux boot
Step 4.6 Set up environment variables
Step 4.7 Run application
Limitations
Support
License
AI Engine Debug with AI Engine Emulator
1. AI Engine Emulator Source Code Debug
Step 1. Select AI Engine Configuration
Step 2. Build with AI Engine Emulator
Step 3. Debug with AI Engine Emulator
Step 4. Source Code Debug with AI Engine Emulator
Step 5. Verify Result
AI Engine emulator source code debug limitations
2. AI Engine Emulator Trace and Profile Data Generation
Step 1: Configuration Before Launching AI Engine Simulator
Step 2: Launch AI Engine Emulator
Step 3: Launch Vitis Analyzer
3. AI Engine Emulator printf Support
Step 1. Add printf statement in source code
Step 2. Build the Project
Step 3. Enable printf in Run Configuration
Step 4. Run the Project
Step 5. Expected result
printf Limitations
4. AI Engine Emulator --enable-memory-check Option
Step 1. Identify an Invalid Address from Design
Step 2. Add access to an invalid memory address
Step 3. Build the application
Step 4. Add --enable-memory-check option in build configuration
Step 5. Run the application
Step 6. Expected result
Step 7. Additional test
Step 8. Clean up
5. Command line project source code debug with AI Engine emulator
Step 1. Download the project
Step 2. Build the Command-Line Project with Debug Capabilities
Step 3. Launch Hardware Emulator and Boot Petalinux
Step 4. Run Host Application from Emulation Console
Step 5. Launch Vitis IDE and XRT Server
Step 6. Expected Vitis IDE
Step 7. Clean up Launched Processes
Support
License
AI Engine Source Code Debug with Hardware Emulator
Hardware Emulation Source Code Debug
Step 1 Build
Step 2 Launch Hardware Emulator
Step 3 During Debug
Step 3.1 Debug - PS
Step 3.2 Debug - AI Engine
Hardware Emulation Source Code Debug Limitations
Command-Line Project Source Code Debug with Hardware Emulator
Step 1 Build Project to be Debugged
Step 2 Launch Hardware Emulator and Boot Petalinux
Step 3 Launch Vitis IDE and XRT server
Step 4 Setup Vitis AI Engine Debug Configuration
Step 4.1 Configure Debug using Click-on Debug Icon
Step 4.2 Under “Single Application Debug” to Create a New Debug Configuration
Step 4.3 Setup New Debug Type Name and Connection
Step 4.4 Setup New Connection Name, Host, and Port
Step 4.5 Setup Execute Script of Newly Created Debug Type
Step 4.6 Close the debug configuration
Step 4.7 Run PS (by resume) Application so AI Engine can be Initialized and Debugged
Step 4.8 Wait until PS has Initialized AI Engine and Observe “Starting graph run” from the Console
Step 4.9 Launch AI Engine Debugger to Debug the AI Engine Sub-project
Step 5 Expected Vitis IDE
Step 6 Clean up Launched Processes
Support
License
AI Engine Source Code Debug on Hardware
Source Code Debug on Hardware
Step 1. Setup Connection to the Hardware Board
Step 1.1. Target Connection Setup
Run hardware server from computer that connects to target board
Step 1.2. Vitis IDE Setup
Step 1.3. Target Connection Verification
Step 2. Debug Project in Vitis IDE
Step 2.1. Target Preparation
Step 2.2. Launch debugger
Limitations of Source Code Debug on Hardware
Support
License
System Project Debug Tutorial with Event Trace
Introduction
Overview
Event Trace Build Options, Generation and Visualization
Step 1. Download tutorial source code
Step 2. Setup build environmental variables
Step 3. Build the tutorial
Step 4. Prepare hardware board
Step 5. Event trace generation
Step 5.1. Event trace with XSDB flow
Step 5.2. Event Trace with XRT flow
Step 6 to Run Application after Petalinux Boots up on Board
Step 7. Collect Event Trace Files
Step 7.1. XSDB Flow
Step 7.2. XRT Flow
Step 8. Launch Vitis Analyzer to Examine Event Trace Files
Event Trace Data Explanation
Event Trace Considerations
Event Trace Choice Considerations
Number of Event Trace Streams Methodology
Event Trace Limitations
Support
License
AI Engine/PL Kernel Debug with XRT Utilities on HW
xbutil
Report AI Engine Status
Step 0 Prepare the boot image and boot the board
Step 1.1 Generate AI Engine status data
Step 1.2 to Run Application after Petalinux Boots up on Board
Step 1.3 Collect AI Engine Status Files
Step 1.3.1
Step 1.3.2
Step 1.3.3
Step 1.4 Launch Vitis Analyzer to Examine Status Files
AI Engine Status Explanation
Report XRT Errors
Report Mechanism with XRT APIs
Step 2.1 Replace host.cpp with host.cpp.error_code that is available from this tutorial.
Step 2.2 Compile the host.cpp code and package to sd_card.img by issuing the following commands.
Step 2.3 Follow step 0 Prepare the boot image and boot the board
Step 2.4 After VCK190 is powered up and booted up complete, run the binaries.
Step 2.5 Expected result is as follows.
Step 2.6 Report Mechanism with xbutil
Support
License
Profiling Graph Inputs and Outputs with Profiling APIs
Overview
Profiling APIs
1. Profiling APIs with AI Engine Simulator
Step 1.1 Download the Project
Step 1.2 Prepare Profiling APIs applied graph code
Step 1.3 Run AI Engine Simulator
Step 1.4 Expected Result
2. Profiling APIs with HW Emulator
Step 2.1 Prepare profiling APIs applied host code and Makefile
Step 2.2 Build the Design
Step 2.3 Run Hardware Emulator
Step 2.4 Run Application
3. Profiling APIs on HW
Step 3.1 Prepare HW Makefile
Step 3.2 Flash SD card
Step 3.3 Boots up VCK190 board
Step 3.4 Run the Application
Step 3.5 Expected result
4. Cross Check I/O Performance values with VCD
Step 4.1 VCD generation
Step 4.2 Launch Vitis Analyzer to view trace
Step 4.3 Locate profiled interface
Step 4.4 Locate tile
Step 4.5 Use tool to measure execution time
Step 4.6 Performance Calculation
Limitations
Support
License
AI Engine Debug with Hardware Profiling Features
Overview
Hardware Profiling Features
XRT Flow
Step 1.1 Prepare the boot image and boot the board
Step 1.2 Generate Profiling data
Step 1.3 to Run Application after Petalinux Boots up on Board
Step 1.4 Collect Profiling Files
Step 1.4.1
Step 1.4.2
Step 1.4.3
Step 1.5 Launch Vitis Analyzer to Examine Profiling Files
XSDB Flow
Step 2.1 Prepare the boot image and boot the board
Step 2.2 Generate Profiling data
Step 2.2.1 Target Connection Setup
Step 2.2.2 Connect XSDB to Board
Step 2.3 to Run Application after Petalinux Boots up on Board
Step 2.4 Inspect generated Files
Step 2.5 Launch Vitis Analyzer to Examine Profiling Files
Step 3 Expected Result with Vitis_Analyzer
Step 4 Open Multiple Profiling Runs with Vitis Analyzer
Step 4.1 Generate First Profiling Data
Step 4.2 Generate Second Profiling Data
Step 4.3 Open First Profiling Data
Step 4.4 Open Second Profiling Data
Profiling Data Explanation
AI Engine core profiling data
AI Engine memory profiling data
Interface profiling data
Profiling Data Analysis
Support
License
AI Engine Debug with Integrated Logic Analyzer (ILA)
AI Engine Debug with Integrated Logic Analyzer (ILA)
Enable ILA in design
Step 1. Prepare the ILA enabled Makefile.
Step 2. Build the ILA enabled design
Step 3. Boot up the design
Setup the connection with Vivado
Step 4. Setup Connection to the Hardware Board
Step 4.1. Target Connection Setup
Step 4.2. Launch Vivado
Step 4.3. Setup Vivado Hardware Manager
Step 4.4. Setup Hardware Target
Step 4.5. Input Hardware Target
Step 4.6. Check Hardware Target
Step 4.7. Select probe file
Step 4.8. Select ILA to be examined.
Step 4.9. Setup design’s signals to be debugged
Step 4.10. Enable ILA to capture the configured signals to debug
Step 4.11. Expected result
Step 5. Examine captured results
Support
License
AI Engine DSP Library and Model Composer
Introduction
Before You Begin
Overview
Stage 1: Create and Simulate the Design
Stage 2: Further Analysis of the Design
Stage 3: Generate the Code and Perform Emulation-AI Engine
Stage 4: Increasing PLIO bitwidth and re-generate
Conclusion
Versal Emulation Waveform Analysis
Introduction
Objectives
Tutorial Overview
Design Overview
Transaction Level Modeling
Steps
Step 1: Build Design
Step 2: Launching Emulation with XSIM Waveform GUI
Step 3: Using XSIM Waveform GUI and QEMU
Exploring the Waveforms
Checking Proper Boot-up Using PMC
Transactions generated by PS (QEMU) to PL/AIE
PL to AI Engine
AI Engine RTP Signals
AI Engine to PL to DDR Memory
Limitations
Step 4: Using Vitis Analyzer
Summary
AXIS External Traffic Generator
Introduction
Objectives
Prerequisites
Tutorial Overview
Directory Structure
Before You Begin
Documentation: Explore AI Engine Architecture
Tools: Installing the Tools
Environment: Setting Up Your Target Platform Environment
Validation: Python Environment
Other Tutorials: Learn Basic Vitis Compiler and AI Engine Concepts
System View
Connecting the AXI Traffic XOs
Understanding Python
Creating a Sine Wave Data Vector
Convert Numpy to Byte Array
Generate AXI Transactions
Receive AI Engine Array Output
Convert Byte Array to Numpy
Plot the results
Running Hardware Emulation
AI Engine and Versal Integration
Section 1: Compile Kernels and AI Engine Graph
Compiling the kernel Files Using v++
Compiling an AI Engine ADF Graph for V++ Flow
Connecting the traffic generators with V++
Section 3: Compile the A72 Host Application
Section 4: Package the Design
Section 5: Run Hardware Emulation
Summary
Support
License
AI Engine Performance and Deadlock Analysis Tutorial
AI Engine Graph Execution and Measurement
Graph and Kernel Code
Graph Execution Model
Graph Performance Measurement
Design Optimization Considerations
Conclusion
Support
License
AI Engine Deadlock Analysis
Common Deadlock Scenarios
AI Engine Deadlock Example and Analysis in AI Engine Simulator
AI Engine Stall Analysis with Vitis Analyzer
AI Engine Deadlock Detection in the Hardware Emulation Flow
AI Engine Deadlock Detection in the Hardware Flow
Conclusion
Appendix (Optional)
Manual Dump and Register Reading to Detect AI Engine Status in Hardware Emulation and Hardware
Support
License
AI Engine Status Analysis
Setting Up and Running the Design
Option 1: Automated and Periodic AI Engine Status Output
Analyzing the Automated Status Output
Option 2: Manual output the AI Engine status
Analyzing the Manual Status Output
Conclusion
Support
License
Implementing an IIR Filter on the AI Engine
Part1a
Implementing an IIR Filter on the AI Engine - Part 1a
Preliminaries
Kernel Code
Julia Script Notes
Adaptive Dataflow Graph
Testbench Code
Build and Run the Program
Conclusion
References
Support
License
Part1b
Recap
Julia Script
Adaptive Dataflow (ADF) Graph
Testbench Code
Building and Running the Design
Changing Coefficients During Runtime
Conclusion
Support
License
Part2a
Implementing an IIR Filter on the AI Engine - Part 2a
Preliminaries
Kernel Code
Testbench Code
Analysis
Conclusion
Support
License
Part2b
Implementing an IIR Filter on the AI Engine - Part 2b
Preliminaries
Kernel Header
Kernel Code (AI Engine API)
Graph Code
Testbench Code
Analysis (using AI Engine API)
Generated Code
Throughput
Kernel Code (LLI)
Conclusions
Support
License
Post-Link Recompile of an AI Engine Application
Lab 1: Direct AI Engine Recompile Makefile Flow
Initialization
Phase 1: Compile AI Engine application and PL Kernels and Link the System
Phase 2: Recompile the AI Engine Application, Package the New System, and Rerun Hardware Emulation
Perform On-Board Testing
Support
License
Lab 2: Vitis Makefile Flow
Initialization
Phase 1: Creating a Fixed Platform from an AI Engine Application and PL Kernels
Phase 2: Using a Platform Generated by Vitis and Modifying the AI Engine Application
Perform On-Board Testing
Support
License
Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows
Introduction
Objectives
Before You Begin
Python Environment Setup
Design Overview
Tutorial Steps
Step 1: ADF Graph Modifications
Step 2: Linking for Hardware Emulation
Step 3: External Traffic Generators
Python Scripts
Script Analysis
Instantiating the XTLM Utilies
Transmitting Data through the ipc_axis_master_util Utility
Receiving Data through the ipc_axis_slave_util Utility
C++ Application
Step 4: Testing the Functionalities
Summary
Support
License
Using RTL IP with AI Engines
Introduction
Objectives
Tutorial Overview
Step 1 - Creating custom RTL kernels with the Vivado® Design Suite
Step 2 - Creating HLS kernels with Vitis® compiler
Step 3 - Interfacing ADF graph to Programmable Logic
Step 4 - Building XCLBIN
Step 5 - Build Host Application
Step 6 - Package
Step 7 - Run Emulation
To View Emulation Waveforms
Summary
License
Using Verilog Traffic Generators in AIE Simulation
Introduction
Objectives
Before You Begin
Documentation
Explore AI Engine Architecture
Traffic Generator
Installing the Tools
Tutorial Overview
Section 1: Overview of the design that will be used in this tutorial.
Directory Structure
Section 2: How to integrate external RTL (Verilog/SV) based traffic generator with AIE.
Generating AIE wrapper stub module
Adding user RTL and external testbench
Instantiating aie wrapper in the external testbench
Generating sim_ipc_axis IPs for vivado project
Section 3: Launch the external process with AIEsim process
Section 4: External RTL simulation in XSIM and other third party simulator support
Section 5: More on Traffic Generators
Summary
Support
License
Design Tutorials
LeNet
Introduction
Tutorial Overview
Before You Begin
Tools: Installing the Tools
Environment: Setting Up the Shell Environment
Super Sampling Rate FIR Filters
Single-Kernel FIR Filter Implementation
Single-Kernel FIR Filter Implementation
Filter Description
<<<<<<< HEAD
Designing the Kernel
Interfaces
Data and Coefficients Management
Coefficients and Data Update Scheduling
Compilation and Analysis
Multi-Kernel FIR Filter Implementation
Designing the Kernel
C++ Code Analysis
Data and Coefficients Management and Operation Scheduling
Compilation and Analysis
Single-Stream Interface
Single-Stream Interface
Super Sampling Rate FIR Filter
Super Sampling Rate and Polyphase
Organize Computation for a 2 Gsps Data Stream in 2 Phases
Designing the Graph
C++ Code Analysis
Compilation and Analysis
Vitis Model Composer implementation
Super Sampling Rate FIR Filter with Dual-Stream Input
Super Sampling Rate FIR Filter with Dual-Stream Input
Dual-Stream Input Impact
Designing the Graph
C++ Code Analysis
Compilation and Analysis
Vitis Model Composer Implementation
Beamforming
Module 01: Custom Platform
Options Table
Dependencies
Build Products
Introduction: What is a Custom Vitis Embedded Platform?
What is the Hardware Platform?
What is the Software Platform?
Platform Vivado Project
Create Platform Vivado Project
Create Block Design
Port Instantiation
AI Engine
AXI Debug Hub IP and Simulation Clock and Reset Generator IP
AXI SmartConnects
AXI Verification IPs
Clock Infrastructure
CIPS
NoC
Create Interface Connections
Clock Connections
AXI SmartConnect Connections
CIPS and NoC Connections
NoC Connections
Clocking Infrastructure Connections
CIPS Clocks
Create Address Segments
Set Platform Attributes
Control Interfaces Requirements
Memory Interface Requirements
Clock Requirements
Set Platform Attributes with for Loops
DDR4 Constraints
Create Wrapper for Block Design
Post Link Tcl Commands
Timing Closure
Emulation Setup
Platform Output Type
Wrap Up Vivado Project
Export Hardware XSA*
Software Platform
Platform Create
Domain Create: AI Engine
Domain Create: Linux
BIF File
Boot Directory
Domain Create: Bare Metal
Generate Platform
References
Support
License
Module 02: AI Engine Design
Options Table
Dependencies
Build Products
Introduction
AI Engine Kernels, Graphs, and Applications
AI Engine Kernels and Graphs
Cascading Chain Subgraph
Downlink Subgraph
Uplink Subgraph
Test Beamforming Graph
AI Engine Application
Sending Data to the Beamforming Kernels
AI Engine Kernels Parameters
AI Engine Subgraph Window Connections
AI Engine Application Data Files
Simulating the AI Engine Graph Application
Run-Time Event API for Performance Profiling
Conclusion
References
Support
License
Module 03: PL Design
Dependencies
PL Master Kernels
PL Slave Kernels
Build Products
PL Kernels: Master and Slaves
PL Master Kernels
PL Master Execution Flow
Reset
Configuration
BLOCK_SIZE
NITER and ROLLOVER_ADDR
Start
Done
IP Kernelization
PL Slave Kernels
PL Slave Execution Flow
Reset
Configuration
BLOCK_SIZE
NITER and ROLLOVER_ADDR
Start
Done
AXI4-Stream Register Slice
Beamforming Design: Downlink AI Engine Graph
Beamforming Design: Uplink AI Engine Graph
References
Support
License
Module 03: sim
Summary
Block diagram of test design
Resources
Module 04: AI Engine and PL Integration
Building the Design
Build XCLBIN from Scratch
Options
Dependencies
Build Products
Introduction: Linking the System
Timing Failure
REV0: vck190_v1_0_wrapper_timing_summary_routed.rpt
REV1: vck190_v1_0_wrapper_timing_summary_routed.rpt
REV0 Configuration File (config.ini)
[connectivity] Section
Number of Kernels
Streaming Connections
[clock] Section
[advanced] Section
New XSA Platform: rev0
Timing Closure
Timing Closure Strategy
REV1: Configuration File (config_2regslice.ini)
[connectivity] Section
[clock] Section
[vivado] Section
New XSA Platform: rev1
References
Support
License
Module 05: Bare-Metal PS Host Application
Introduction: Building a Bare-Metal System
Building the Design
Difference between main_partial.cpp and main_full.cpp
Generating the Platform
Compiling the PS Application Source Code
Linking the PS Application Source Code
Bare-Metal Source Code
PS Host Application
Main Function
test_dlbf/test_ulbf Functions
Reset
Configuration
Check RAM
Start
Wait for Done: Inputs
Wait for Done: Outputs
Verify Output
Test ULBF
References
Support
License
Module 06: System Integration: Bare Metal
Building the Design: Hardware Emulation
Dependencies
Build Products
Running the System: Hardware Emulation
Building the Design: Hardware
Dependencies
Build Products
Running the System: Hardware
References
Support
License
Module 07: PetaLinux
Differences between Bare Metal and PetaLinux
Building the Design
Building the PetaLinux Software Platform
Create PetaLinux: Creating the PetaLinux Project with a BSP
Config PetaLinux: Updating the PetaLinux Project with an XSA
Config PetaLinux: Customizing the Root File System
Config Petalinux: Updating the Device Tree
Config Petalinux: Customizing Kernel Configuration
Config Petalinux: Clean-Up
Build PetaLinux: Building the PetaLinux Image
Build Petalinux: Building the SDK (Target Sysroot Generation)
Build PetaLinux: Installing the SDK (Target Sysroot Generation)
Build PetaLinux: Generating the Boot Image
Build the Versal Custom PetaLinux Platform
References
Support
License
Module 07: PetaLinux boot
Module 08: Linux SW Application
Introduction: Programming the PS Host Application
Execution Flow Chart
Bind UIO Drivers with PL Kernels
Changes in 2022.2
Load AIE XCLBIN
Reset AI Engine
Load AI Engine with XCLBIN
Reset AI Engine in the Middle of Execution
Command-Line Arguments
Support
License
Module 09: System Integration: Linux
Running the System
Support
License
2D-FFT
AIE
Building the Design
Make Steps
Build the Entire Design with a Single Command
make kernels: Compiling PL Kernels
make graph: Creating the AI Engine ADF Graph for Vitis Compiler Flow
make xsa: Using the Vitis Tools to Link AI Engine and HLS Kernels with the Platform
make application: Compiling the Host Application
make package: Packaging the Design
make run_emu: Running Hardware Emulation
Running on Hardware
Hardware Design Details
Design Details
AI Engine and PL Kernels
dma_hls
Software Design Details
AI Engine Kernels and Graph Representation
Adaptive Data Flow (ADF) Graph
Defining the Graph Class
Top-Level Application
PL Data Mover Kernel
dma_hls (dma_hls.cpp)
Top Function Declaration
Top Function Definition
PS Host Application
HLS
Building the Design
Make Steps
Build the Entire Design with a Single Command
make kernels: Compile PL Kernels
make xsa: Using the Vitis Tools to Link HLS Kernels with the Platform
make application: Compile the Host Application
make package: Packaging the Design
make run_emu: Running Hardware Emulation
Running on Hardware
Hardware Design Details
Design Details
HLS/PL Kernels
FFT_2D
DMA_HLS
Software Design Details
HLS/DSP Kernel Representation
Data Flow
Define FFT Inputs
Required Headers and Function Declarations
FFT Core Config Structure
Top Function
Sub-Function Details
Reading Data
FFT Function
Writing Out Data
PL Data Mover Kernel
dma_hls (dma_hls.cpp)
Top Function Declaration
Top Function Definition
PS Host Application
FIR Filter
AIE
Building the Design
Make Steps
Build the Entire Design with a Single Command
make kernels: Compile PL Kernels
make graph: Creating the AI Engine ADF Graph for Vitis Compiler Flow
make xsa: Use Vitis Tools to Link AI Engine and HLS Kernels with the Platform
make application: Compile the Host Application
make package: Package the Design
make run_emu: Run Hardware Emulation
Run on Hardware
Hardware Design Details
Design Details
AI Engine and PL Kernels
Software Design Details
Data Flow Graph
Define the Graph Class
Instantiate DSPLib FIR Filters
Add Connectivity Information
Top Level Application
Simulator Control
PL Kernels
datamover (datamover.cpp)
Arguments
pragma HLS INTERFACE s_axilite
pragma HLS INTERFACE axis
pragma HLS PIPELINE II=1
PS Host Application
Include graph.cpp
load_xclbin Function
Datamover Class
FIR Chain Class
Main Function
1. Check Command Line Argument
2. Open XCLBIN
3. Create and Initialize Data Mover Kernels and FIR Chain Graph
4. Run the Data Mover Kernel and FIR Chain Graph
5. Wait for Data Mover Kernels to Complete
6. Verify Output Results
7. Release Allocated Resources
References
AI Engine Documentation
Support
License
HLS
Building the Design
Make Steps
Build the Entire Design with a Single Command
make kernels: Compile PL Kernels
make xsa: Use Vitis Tools to Link HLS Kernels with the Platform
make application: Compile the Host Application
make package: Package the Design
make run_emu: Run Hardware Emulation
Run on Hardware
Hardware Design Details
Design Details
HLS PL Kernels
Software Design Details
N-Body Simulator
Running the Simulation
Python Simulations on x86 Machine
Results
(Optional) Creating Animation GiFs
Next Steps
Support
License
Build the Design
AI Engine Design
A Single Nbody() Kernel
Four NBody() Kernels Packet Switched
Workload Distribution and input_j
100 N-Body Subsystems
Why Packet Switching?
(Optional) Simulate the AI Engine Design
References
Next Steps
Support
License
Building the Design
Step 1: Download the Vitis Utility Library
Step 2: Generate m2s_x2.cpp and s2m_x4.cpp Datamover kernels
Step 3: Compile HLS PL Kernels
HLS PL Kernels
m2s_x2
packet_sender
packet_receiver
s2m_x4
References
Next Steps
Support
License
Full System Design
Full System Design
Design Implementation
References
Next Steps
Support
License
Host Software
Step 1: Compile Host Software
Step 2: Link Host Software
Host Software
NBodySimulator API
Logger API
Log Levels:
Host Applications
References
Next Steps
SD Card Image Generation and Hardware Run
SD Card Image Generation
Booting the VCK190 Board
Running the Design on Hardware
References
Next Steps
Support
License
Results
Results
12,800 Particles Simulated on a 400 tile AI Engine Accelerator for 300 Timesteps
Latency Performance Comparisons
Design Throughput Calculations (Effective vs. Theoretical)
(Optional) Building x1_design and x10_design
Building the x1_design (simulates 128 particles)
Building the x10_design (simulates 1,280 particles)
Support
License
x10 Design Results
x1 Design Results
FIR Filter
AIE
Building the Design
Make Steps
Build the Entire Design with a Single Command
make kernels: Compiling PL Kernels
make graph: Creating the AI Engine ADF Graph for Vitis Compiler Flow
make xclbin: Using the Vitis Tools to Link AI Engine and HLS Kernels with the Platform
make application: Compiling the Host Application
make package: Packaging the Design
make run_emu: Running Hardware Emulation
Running on Hardware
Hardware Design Details
Design Details
AI Engine and PL Kernels
dma_hls
Software Design Details
HLS
Building the Design
Make Steps
Build the Entire Design with a Single Command
make kernels: Generates the PL Kernels
make xsa: Using the Vitis Tools to Link HLS Kernels with the Platform
make application: Compile the Host Application
make package: Packaging the Design
make run_emu: Running Hardware Emulation
Running on Hardware
Hardware Design Details
PL Kernel Details
Platform Details
Software Design Details

Version: Vitis 2022.2

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