nk switch is added, which creates 528
axi4s_regslice PL kernels. In Module 03, you compiled the XO for the
axi4s_regslice PL kernel definition.
sc switches are also altered so that there are two
axi4s_regslice_64b kernels between the PL kernels and AI Engine. The following snippet is an example of how this is done.
sc=dlbf_data_00.M00_AXIS:axi4s_regslice_64b_1.S_AXIS sc=axi4s_regslice_64b_1.M_AXIS:axi4s_regslice_64b_2.S_AXIS sc=axi4s_regslice_64b_2.M_AXIS:ai_engine_0.dlbfid0