dma_hls - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

The PL-based data mover consists of the dma_hls kernel, which generates constant Inputs for Mat A and B and checks the output of GeMM graph for the expected constant pattern.

  • It internally comprises four loops (inp_A, inp_B, and out_C), with all concurrently scheduled.

  • The data width is 128 bits at both the AXI4-stream I/O sides, running at 250 MHz.