After the kernel is generated, you can use the Vitis compiler to link it with the platform to generate an XSA file.
The Vitis tools allow you to integrate the kernels into an existing extensible platform. This is an automated step from a software developer perspective where the platform chosen is provided by the hardware designer (or you can opt to use one of the many extensible base platforms provided by Xilinx and the Vitis tools build the hardware design and integrate the kernels into the design).
The command to run this step is shown as follows
make xsa TARGET=<hw/hw_emu> GEMM_SIZE=<64,128,256,512,1024>
The expanded command is as follows:
cd $(BUILD_TARGET_DIR); \
v++ -l --platform xilinx_vck190_base_202320_1 --save-temps --temp_dir $(BUILD_TARGET_DIR)/_x \
--verbose -g --clock.freqHz 500000000:gemm_large_ocm_0 --clock.defaultTolerance 0.001 \
--config $(SYSTEM_CONFIGS_REPO)/gemm.cfg --vivado.prop fileset.sim_1.xsim.simulate.log_all_signals=true \
--vivado.prop run.synth_1.{STEPS.SYNTH_DESIGN.ARGS.CONTROL_SET_OPT_THRESHOLD}={16} \
--vivado.prop run.synth_1.{STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS}={true} \
--xp vivado_prop:run.impl_1.STEPS.PLACE_DESIGN.TCL.PRE=$(CONSTRAINTS_REPO)/gemm_dsp58.tcl
-t hw_emu -o $(BUILD_TARGET_DIR)/gemm.hw_emu.xclbin $(PROJECT_REPO)/build/gemm_GEMM_SIZExGEMM_SIZExGEMM_SIZE/gemm_large_ocm.xo
See this page for a detailed description of Vitis linking options. The following table provides a summary of the switches used.
| Switch | Description |
|---|---|
| --platform | -f | Specifies the name of a supported acceleration platform as specified by the $PLATFORM_REPO_PATHS environment variable or the full path to the platform XPFM file. |
| --save-temps | -s | Directs the V++ command to save intermediate files/directories created during the compilation and link process. Use the --temp_dir option to specify a location to write the intermediate files to. |
| --temp_dir |
This allows you to manage the location where the tool writes temporary files created during the build process. The temporary results are written by the Vitis compiler, and then removed, unless the --save-temps option is also specified. |
| --verbose | Display verbose/debug information. |
| --output | -o | Specifies the name of the output file generated by the V++ command. In this design the outputs of the HLS/DSP kernels with their interfacing with the PL kernels are in XO files. |
| --vivado.prop \<arg> | Specifies properties for the Vivado Design Suite to be used during synthesis and implementation of the FPGA binary (xclbin). See this page for detailed Vivado options. |
| --profile.data [ |
Enables monitoring of data ports through the monitor IPs. This option needs to be specified during linking. See this page for detailed profiling options. |
| --profile.trace_memory \<FIFO>:\<size>|\<MEMORY>[\<n>] | When building the hardware target (-t=hw), use this option to specify the type and amount of memory to use for capturing trace data. See this page for detailed profiling options. |
| --config |
Specifies a configuration file containing V++ switches. |
The information to tell the linker how to connect the PL kernels together is described in a configuration file, system_configs/gemm.cfg. The file describes the overall connection scheme of the system.
[connectivity]
nk=gemm_large_ocm:1:gemm_large_ocm_0
[clock]
id=0:gemm_large_ocm_0.S_AXI_ACLK
[advanced]
## Disable Profiling in hw_emu so that it is faster...
param=hw_emu.enableProfiling=false
## Export the xsa of the design..
param=compiler.addOutputTypes=hw_export
param=compiler.worstNegativeSlack=-1.0
[vivado]
prop=run.synth_1.STRATEGY=Flow_PerfOptimized_high
prop=run.impl_1.STEPS.OPT_DESIGN.is_enabled=true
prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore
prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=ExtraTimingOpt
prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.is_enabled=true
prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
#prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS=-tns_cleanup
prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
See this page for a detailed description of the Vitis compiler configuration file. A summary of the configuration options used is provided in the following table.
| Switch | Comment |
|---|---|
| --connectivity.nk | Number of kernels. gemm_large_ocm:1:gemm_large_ocm_0 means that the Vitis compiler should instantiate one gemm_large_ocm kernel and name the instance gemm_large_ocm_0. |
| param=hw_emu.enableProfiling=false - This option disables profiing during hw_emu for faster run time | |
| param=compiler.addOutputTypes=hw_export | This option tells the Vitis compiler that besides creating an XCLBIN file, it also outputs an XSA file which is needed to create a post-Vivado fixed platform for Vitis software development. |
| param=compiler.worstNegativeSlack=-1.0 - This parameter sets 210ps tolerance for WNS | |
| prop=run.synth_1.STRATEGY=Flow_PerfOptimized_high - This parameter sets Synthesis streategy | |
| prop=run.impl_1.STEPS.OPT_DESIGN.is_enabled=true - This option enables opt design directive | |
| prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore - This option sets the value of opt design stage directive | |
| prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=ExtraTimingOpt - This option sets the value of place design directive | |
| prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.is_enabled=true - This option enables physical optimzation directive | |
| prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore - This option sets value of physical optimization directive | |
| prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=AggressiveExplore - This option sets value of route design directive |
The Vitis™ compiler calls the Vivado™ IP integrator under the hood to build the design. The platform and kernels are input to the Vivado Design Suite, which produces a simulation XSA or an XSA after running place and route on the design. The point at which the XSA is produced from Vivado depends on the -target option set on the Vitis compiler command line.
You can now view the Vivado project, which is located in the $(BUILD_TARGET_DIR)/_x/link/vivado/vpl/prj directory. You have now generated the XCLBIN file, $(BUILD_TARGET_DIR)/gemm.hw_emu.xclbin, that is used to execute your design on the platform.