In the Vitis Components Explorer select the new cloned components,
dct-dataflowin this example, and select the
hls_config.cfgfile of the cloned component to open it.
In the Config Editor select Add Item for Dataflow to open the Directive Editor. In the HLS Directive view navigate to the
dctfunction and select Add Directive.
In the Add Directive dialog box select the DATAFLOW pragma, and specify Config File as the location to add
Rerun synthesis and review the reports.
Notice that the Synthesis Summary report now displays a negative value in the Slack column, indicating a potential timing violation in the generated RTL design. As described in Running Implementation, the HLS compiler reports the results of high-level synthesis providing an estimate of the results with projected clock frequencies, timing, and resource utilization (LUTs, DSPs, BRAMs, etc). However, these results are only estimates because the tool cannot know what optimizations or routing delays will be in the final synthesized or implemented design. A more accurate estimate of the resources and timing of the RTL design can be provided by runing the design through synthesis or implementation in the Vivdao Design Suite. You will do this shortly to check the timing of the design.
You should also notice the addition of the Dataflow Viewer report as a result of adding the Dataflow directive. However, as explained in Dataflow Viewer, you must run C/RTL Co-simulation in order to get details from the dataflow design. Examine the Dataflow Viewer report prior to running Co-simulation, and then again after. First you should configure the Co-simulation to perform as you want.