ACTION: Back out the prior change before proceeding. Depending on whether you added PIPELINE as a pragma to the source code, or a directive to the config file, you can remove it from the appropriate location. You can also select the pragma in the HLS Directive view and delete it from there.
In some designs, a Guidance message
Unable to schedule load operation... indicates a load/load (or read/read conflict) issue with memory transactions. In these cases rather than accepting the latency, you could try to optimize the implementation to achieve the best performance (II=1).
The specific problem of reading or writing to memory can possibly be addressed by increasing the available memory ports to read from, or to write to. One approach is to use the BIND_STORAGE pragma or directive to specify the type of device resource to use in implementing the storage. BIND_STORAGE defines a specific device resource for use in implementing a storage structure associated with a variable in the RTL. For more information, refer to BIND_STORAGE.
Looking at the Storage Report section of the Synthesis report you can see that the tool has implemented the
buf_2d_in variable with a
ram_s2p. This allows reading on one port while writing on the other. But the RAM_2P allows simultaneous reading on both ports, or reading on one and writing on the other. This might offer some performance improvement.
In the Config Editor select Add Item for Bind Storage to open the Directive Editor. In the HLS Directive view navigate to the
dctfunction, select the buf_2d_in variable, and select Add Directive.
In the Add Directive dialog box select the BIND_STORAGE pragma, specify type of
ram_2pand impl of
bram, and click OK to add the directive or pragma to your design.
TIP: You can also edit the
hls_config.cfg file and add the following line directly:
syn.directive.bind_storage=dct buf_2d_in impl=bram type=ram_2p
Run C Synthesis again and examine the results.