ACTION: Back out the change before proceeding. Select the source code tab to make it active and display the Directive view. Right-click HLS PIPELINE II=4 and select Remove Directive.
In some designs, a Guidance message
Unable to schedule load operation... indicates a load/load (or read/read conflict) issue with memory transactions. In these cases rather than accepting the latency, you could try to optimize the implementation to achieve the best performance (II=1).
The specific problem of reading or writing to memory can possibly be addressed by increasing the available memory ports to read from, or to write to. One approach is to use the BIND_STORAGE pragma or directive to specify the type of device resource to use in implementing the storage. BIND_STORAGE defines a specific device resource for use in implementing a storage structure associated with a variable in the RTL. For more information, refer to BIND_STORAGE in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
Select the dct.cpp tab to make the Code Editor active.
In the Directives view, right-click on the
col_inbufvariable in the
dct_2dfunction, and select Insert Directive.
This displays the Vitis HLS Directive Editor.
For Directive, select BIND_STORAGE.
For Destination, select Directive File.
In Options, the variable you selected is listed. Specify the type of memory to use for the variable as dual-port RAM,
ram_2p, and specify the implementation as
You can optionally specify the latency, but leave it blank for now.
Repeat the process for the the
buf_2d_outvariable of the top-level
In the Directive view, select the
buf_2d_outvariable and add the BIND_STORAGE pragma to specify the dual-port RAM
ram_2p, and implementation
Click Run C Synthesis to rerun synthesis to see the results.