Create and run a HLS project - 2022.2 English

Vitis Tutorials: Getting Started

Document ID
XD098
Release Date
2022-11-07
Version
2022.2 English

In this step, we are going to create a HLS project by using the files provided in the 1Dfix_impluse example of L1 Vitis dsp library. The source files and script file are all located under this folder. Here we assume you have cloned the Vitis Libraries into /home/project/Vitis_Libraries directory.

  1. Go into the /home/project/Vitis_libraries/dsp/L1/examples/1Dfix_impluse folder and run below command to create the HLS project.

 make run CSIM=1 CSYNTH=1 COSIM=1 XPART=xcvu9p-flgc2104-2-e

By executing the command it will run through project creation, C synthesis, C simulation and Co-simulation flow. You can modify the parameter to skip certain steps. Here the xcvu9p part is used as an example, you may change it to other FPGA parts. Or you can use DEVICE keyword to specify an acceleration platform such as u250 Alveo platform. At the end of the flow, console window will print out the input and output data value and show PASS at the end of simulation.

...

===============================================================
--Input Impulse:
(1,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
===============================================================
===============================================================
--Output Step fuction:
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
===============================================================
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***

...

The testbench uses a single pulse signal as input to the FFT and the output should be a step signal. And these can be verified by looking at the values printed out to the screen.

  1. Now we will open the project in Vitis HLS GUI. Enter following command in /home/project/Vitis_libraries/dsp/L1/examples/1Dfix_impluse directory:

vitis_hls -p prj_impulse_test.prj &

You may browse into the source files, synthesis report or waveform viewer by simply selecting them from the ‘Explorer’ window and ‘Flow Navigator’ window.

The top_module.cpp calls the FFT library and the parameters are defined in the data_path.hpp file. For detailed instructions about how to use FFT library, please refer to the Vitis Library Doc Portal.

  1. Export IP in HLS project

Now we have verified that the library IP is working properly and we will export it to a Vivado IP. To do so, click the Export RTL from IMPLEMENTATION item in Flow Navigator. In the pop-up window, we will leave every settings unchanged and click OK to export the IP. By default, the IP will be exported to the <project folder>/solutionN/impl, in this case, it is in following directory:

/home/project/Vitis_Libraries/dsp/L1/examples/1Dfix_impluse/prj_impulse_test.prj/solution1/impl

However you may customize the path in the export pop-up menu.

In the next step, we will launch Vivado and create a top-level design to instantiate the exported IP. You may close the Vitis HLS GUI now.

  1. View Co-Simulation Waveform (optional)

You could modify the co-simulation related command lines in file ./run_hls.tcl (around line 48) as below to turn-on the xsim waveform dump switch:

...
if {$COSIM == 1} {
  cosim_design -wave_debug
}
...

Then re-run the command:

 make run COSIM=1 XPART=xcvu9p-flgc2104-2-e

In this way you could get the simulation waveform, such as following example for a single SSR stream port:

../../_images/cosim_wave.png

We will use the interface signals behavior in co-simulation waveform as a reference for the following Vivado simulation testbench.