Use the File > New Component > HLS to create a new HLS component. This opens the Create HLS Component wizard to the Name and Location page.
For the Component name field specify
For the Component location specify the workspace which is the default value
Click Next to open the Configuration File page
The Configuration File lets you specify commands for building and running the HLS component as described in HLS Config File Commands. You can specify a new empty file, an existing config file, or generate a config file from an existing HLS project as described in Creating an HLS Component.
Select Empty File and click Next.
This opens the Source Files page.
Select the Add Files icon to open a file browser, navigate to
<tutorial_path>/Getting_Started/Vitis/example/src/vadd.cppand select Open to add the file.
After adding the file you can see fields for adding CFLAGS and CSIMFLAGS for all source files, or specific to each file. Add these to your design if needed.
Under the Top Function browse and select the
vaddfunction and click OK.
TIP: There are no Test bench files for the
vadd kernel, but you will test the kernel later using the software emulation flow of the System project.
Click Next to open the the Select Part page.
Set the radio button to Platform, select the
xilinx_zcu102_base_202320_1platform and click Next to open the Settings page.
On the Settings page specify
8nsfor the clock, and
12%for the clock_uncertainty to override the default values.
For flow_target select the
Vitis Kernel Flow
For package.output.format specify
Generate a Vitis XOto create .xo output`.
The default clock uncertainty, when it is not specified, is 27% of the clock period. For more information, refer to Specifying the Clock Frequency
Click Next to open the Summary page. Review the Summary page and click Finish to create the defined HLS component.
The HLS component is created and opened as shown in the figure below.
In the Vitis Components Explorer you can see the
vadd component created, with the
vitis-comp.json file opened in the center editor. You can see the
hls-config.cfg file which is where the build directives will be placed to control the simulation and synthesis process.
The Flow Navigator displays the
vadd component as the active component, and shows the flow for designing the HLS component including C Simulation, C Synthesis, C/RTL Co-simuation, and Implementation.
One advantage of the unified Vitis IDE is the ability to work from the bottom-up, building your HLS or AIE components and then integrating them into a higher-level system project.