Now that you have learned the basics of the Vitis flow, you can try some experiments on your own. A good place to start is to try making changes to the host program. If you only change the
host.cpp file, then you do not need to rebuild the FPGA binary, which makes for very quick build-and-run iterations.
In the host program, the size of the vectors is hardcoded to 4096 elements (through the DATA_SIZE macro).
What happens if you increase this size to a much larger value?
What do you see in Vitis Analyzer?
The host program only calls the accelerator once.
What happens if you put a loop around Step 4 in
host.cppto iterate a few more times?
How does the Timeline Trace look now?
Can you make it so that the host program sends different vectors to the kernel each time the host calls it?