Running High-Level Synthesis and Analyzing Results - 2023.2 English

Vitis Tutorials: Getting Started (XD098)

Document ID: XD098
Release Date: 2023-11-13
Version: 2023.2 English

Vitis Tutorials: Getting Started
Vitis Introduction and Getting Started
Essential Concepts
Understanding the Vitis Programming and Execution Model
Understanding the Vitis Build Process
Understanding Vitis Build Targets
Next Step
Installation and Configuration
Part 2: Installation and Configuration
Step 1: Review the Installation Requirements
Step 2: Download Vitis
Step 3: Install Downloaded Packages
Step 4: Download and Install the Required Platform files
Step 4A: Installing Data Center Platform Files
Step 4B: Installing Embedded Processor Platform Files
Step 5: Set Up the Environment to Run Vitis
Next Step
Review the Kernel Code and Host Application
Part 3: Review the Kernel Code and Host Application
The Source Code for the Vector-Add Kernel
The Source Code for the Host Program
Next Step
Build and Run the Data Center Application
Part 4: Build and Run the Data Center Application
Building and Running on Alveo U250 Data-Center Accelerator Card
Setting Up the Environment
Targeting Software Emulation
Targeting Hardware Emulation
Targeting Hardware
Next Step
Build and Run the Embedded Processor Application
Part 4: Build and Run the Embedded Processor Application
Building and Running on ZCU102 Zynq MPSoC Embedded Processor Platform
Setting up the environment
Targeting Software Emulation
Targeting Hardware Emulation
Targeting Hardware
Next Step
Build and Run with the New Vitis Unified IDE
Part 4: Build and Run with the Vitis unified IDE
Launch the Vitis unified IDE
Creating the HLS Component
Creating the Application Component
Creating the System Project
Building and Running the System Project
Next Step
Visualizing Results and Viewing Report
Part 5 : Visualizing Results and Analyzing Reports
Locating the Reports and Summaries
Opening the Run Summary with Vitis Analyzer
Homework
Wrap-Up and Next Steps
Vitis HLS
Using the New Vitis Unified IDE
Running High-Level Synthesis and Analyzing Results
Run the C Simulation
Run C Synthesis
Analyze the Results
Next Step
Using Optimization Techniques
Loop Pipeline
Pipeline Directive
Assign Dual-Port RAMs with BIND_STORAGE
Using Array_Partition
Next Step
Reviewing the DATAFLOW Optimization
Clone Component for Design Exploration
Adding the Dataflow Directive
Run C/RTL Co-Simulation
View the Dataflow Graph
Running Implementation to Improve Timing and Resource Estimates
Export the Vitis Kernel
Summary
Vitis Libraries
Before You Begin
Setup Environment
Get Vitis Libraries
Create and run an HLS Component
Use the Exported IP in the Vivado Design Suite
Summary
Reference
Vitis Platform
Step 1: Create Vivado Design and Generate XSA
Step 2: Create Vitis Platform
Step 3: Validate this Vitis PLatform
Run the Application on Hardware
Fast Track

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