To check the timing error that was reported earlier, you can run Vivado Synthesis or Implementation on the RTL design. This lets the Vivado tool provide more detailed analysis of the RTL design after synthesis of the netlist, or place and route of the logic into a device.
In the Config File Editor, select the Implementation heading and specify the
Run only synthesisor
Run full implementation.
max_timing_pathsto set or ensure it is set to the default value of 10 timing paths. This lets the tool return the 10 worst timing paths.
In the Flow Navigator select Run under the Implementation heading.
The Vivado tool is launched with the RTL design, and synthesis and implementation are run on the design. Under the Report heading in the Flow Navigator you will find the RTL Synthesis report or the Place and Route report. Open either and scroll to the bottom to review the Timing Paths section of the report. This should confirm that there is no timing issue with the design.