Step 1: Create Vivado Design and Generate XSA - 2022.2 English

Vitis Tutorials: Getting Started

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2022.2 English
  1. Create a workspace and Launch Vivado if you haven’t

    • mkdir WorkSpace

    • cd WorkSpace

    • Run source <Vitis_Install_Directory>/ to setup Vivado running environment

    • Run Vivado by typing vivado in the console.

  2. Download the Versal Extensible Embedded Platform Example

    • Click menu Tools -> Vivado Store..

    • Click OK to agree to download open source examples from web

    • Select Platform -> Versal Extensible Embedded Platform and click the download button on the tool bar

    • Click Close after installation complete.

    Vivado XHUB download examples

  3. Create the Versal Extensible Embedded Platform Example project

    • Click File -> Project -> Open Example

    • Click Next

    • Select Versal Extensible Embedded Platform in Select Project Template window.

    • Input project name and project location. Keep Create project subdirectory checked. Click Next.

    • Select target board in Default Part window. In this example, we use Versal VCK190 Evaluation Platform .Click Next.

    CED Configuration

    • Configure Clocks Settings. You can enable more clocks, update output frequency and define default clock in this view. In this example, we can keep the default settings.

    • Configure Interrupt Settings. You can choose how many interrupt should this platform support. 63 interrupts mode will use two AXI_INTC in cascade mode. In this example, we can keep the default setting.

    • Configure Memory Settings. By default, the example design will enable the on board DDR4 and LPDDR4. If you have additional on board memories, you can enable it.

    • Click Next.

    • Review the new project summary and click Finish.

    • After a while, you will see the design example has been generated.

    The generated design is like the following:

    Vivado Design Block Diagram

    At this stage, the Vivado block automation has added a Control, Interface & Processing System (shorten with CIPS in the future) block, AXI NOC block, AI Engine, and all supporting logic blocks to the diagram, and applied all board presets for the VCK190. The instantiated axi_smc_vip_hier in purple color is a hierarchy in which smart connects and dummy IPs are packaged together for clear view and better understanding.

  4. Generate Block Diagram

    • Click Generate Block Diagram from Flow Navigator window

    missing image

    • Select Synthesis Options to Global to save generation time.

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    • Click Generate button

    Note: It’s safe to ignore this critical warning. Vitis will connect this signal in the future.

    Intr Critical Warning

  5. Export hardware platform with the following scripts

    • Click File -> Export -> Export Platform. Alternative ways are: Flow Navigator window: IP Integrator -> Export Platform, or the Export Platform button on the bottom of Platform Setup tab.

    • Click Next on Export Hardware Platform page

    • Select Hardware. If there are any IP that doesn’t support simulation, we need to generate Hardware XSA and Hardware Emulation XSA separately. Click Next

    • Select Pre-synthesis, because we’re not making an DFX platform. Click Next

    • Input Name: VCK190_Custom_Platform, click Next

    • Update file name to vck190_custom_hw, click Next.

    • Review the summary. Click Finish.

    • vck190_custom_hw.xsa file will be generated in Vivado project location directory.