A Vitis accelerated application consists of two distinct components: a software program and an FPGA binary containing hardware accelerated kernels.
The software program is written in C/C++ and runs on a conventional CPU. The software program uses user-space APIs implemented by the AMD Runtime library (XRT) to interact with the acceleration kernel in the FPGA device.
The hardware accelerated kernels can be written in C/C++ or RTL (Verilog or VHDL) and run within the programmable logic part of the FPGA device. The kernels are integrated with the Vitis hardware platform using standard AXI interfaces.
Vitis accelerated applications can execute on either data center or embedded acceleration platforms:
On data center platforms, the software program runs on an x86 server, and the kernels run in the FPGA on a PCIe®-attached acceleration card.
On embedded platforms, the software program runs on an ARM processor of a AMD MPSoC device and the kernels run within the same device.
Because the software and hardware components of a Vitis application use standardized interfaces (XRT APIs and AXI protocols) to interact with each other, the user’s source code remains mostly agnostic of platform-specific details and can be easily ported across different acceleration platforms.
There are multiple ways by which the software program can interact with the hardware kernels. The simplest method can be decomposed into the following steps:
The host program writes the data needed by a kernel into the global memory of FPGA device.
The host program sets up the input parameters of the kernel.
The host program triggers the execution of the kernel.
The kernel performs the required computation, accessing global memory to read or write data, as necessary. Kernels can also use streaming connections to communicate with other kernels.
The kernel notifies the host that it has completed its task.
The host program can transfer the data from global memory to host memory or can give ownership of the data to another kernel.