Assuming you are in the root directory for this tutorial.
Create top level project in Vivado using provided RTL source files
Use following command to create a directory and start Vivado GUI:
mkdir vivado cd ./vivado vivado &
Create a new project with default project name project_1 and select the type as RTL Project with Do not specify sources at this time box checked. Select xcvu9p-flgc2104-2-e as the part of this project. You may select other parts as well.
Now the project has been created. Let’s add the source files into the project. Select
Add or create design sources menu from
PROJECT MANAGER >
Add Sources and then click
Add Files to add the fft_wrap.v which is located under src folder. Then select
Add or create simulation sources menu and click
Add Files to add the fft_tb.v into the project. Use the same procedure to add the datain.txt and dataref.txt files into the project as simulation sources as well.
The fft_wrap.v simply instantiates the FFT IP which we just exported earlier. We need to set up the IP repo path in order to let Vivado find it. To do so, click
settings from Flow Navigator panel and add the IP export folder to the repo path.
IP Catalog from Flow Navigator and you should see the FFT IP shown in the User Repository.
Double click on the IP and click
OK to add it into the project. Now you should see the IP core was correctly instantiated in the project hierarchy view.
Open the fft_wrap.v file to take a look at its port signals. Along with the clock, reset and control signals (start, done, idle, ready), there are four input steam ports (inData_x and inData_x_ce) and four output stream ports (outData_x and outData_xwe*). The input and output data bus are simply validated by _ce or _we signals. In the testbench file fft_tb.v, we read the input data from datain.txt file, divide them into four data streams and then send them to the fft module. Four output data streams are received and compared with the reference data file dataref.txt. The test datasets are identical with the simulation example in /home/project/Vitis_Libraries/dsp/L1/examples/1Dfix_impluse directory.
module fft_wrap ( output inData_0_ce, output inData_1_ce, output inData_2_ce, output inData_3_ce, input [31:0] inData_0, input [31:0] inData_1, input [31:0] inData_2, input [31:0] inData_3, output outData_0_we, output outData_1_we, output outData_2_we, output outData_3_we, output [41:0] outData_0, output [41:0] outData_1, output [41:0] outData_2, output [41:0] outData_3, input clk, input rst, input start, output done, output idle, output ready );
Simulate the top level project
Run Simulation from Flow Navigator and select
Run Behavioral Simulation. Vivado simulator launches with waveform loaded. Please note that the input data bus width is 32-bit and output data bus width is 42-bit.
If no issues encountered, simulation will end smoothly.
Result verification SUCCEED! Simulation finished.
Below is the screen shot of the simulation waveform.
Close the simulation window.
Implement the top level project
Run Implementation from Flow Navigator panel and click OK in the pop-up window. This will run through the Vivado synthesis and implementation flow which will generate both timing and resource reports for this IP.