Use the Exported IP in the Vivado Design Suite - 2023.2 English

Vitis Tutorials: Getting Started

Document ID
XD098
Release Date
2023-11-13
Version
2023.2 English

Note: This portion of the tutorial requires you to be in the <installdir>/Vitis_Tutorials/Getting_Started/Vitis_Libraries folder.

  1. Use the following commands to create a top level Vivado project using provided RTL source files:

mkdir vivado
cd ./vivado
vivado &

Create a new project with default project name project_1 and select the type as RTL Project with Do not specify sources at this time box checked. Select xcvu9p-flgc2104-2-e as the part of this project. You can select other parts as well.

Now the project has been created, add the source files into the project.

  • From PROJECT MANAGER > Add Sources select Add or create design sources and click Next

  • Click Add Files to add the fft_wrap.v which is located under src folder of this tutorial.

  • Then select Add or create simulation sources menu and click Add Files to add the fft_tb.v into the project.

  • Use the same procedure to add the datain.txt and dataref.txt files into the project as constraints.

Design Sources

The fft_wrap.v instantiates the fft_top IP that was exported from the HLS component. However, you must first set up the IP repo path to let Vivado find it, and add it to your design. To do so, click Settings from Flow Navigator panel and add the IP export folder to the repo path.

IP Repo

Then click IP Catalog from Flow Navigator and you should see the FFT IP shown in the User Repository.

IP Catalog

Double click on the IP and click OK to add it into the project. Now you should see that the IP core was correctly instantiated in the project hierarchy view.

  1. Open the fft_wrap.v file to take a look at its port signals.

Along with the clock, reset, and control signals (start, done, idle, ready), there are four input steam ports (inData_x and inData_x_ce) and four output stream ports (outData_x and outData_xwe*). The input and output data bus are simply validated by _ce or _we signals. In the testbench file fft_tb.v, read the input data from datain.txt file, divide them into four data streams, and then send them to the fft module. Four output data streams are received and compared with the reference data file dataref.txt. The test datasets are identical with the simulation example in /home/project/Vitis_Libraries/dsp/L1/examples/1Dfix_impluse directory.

module fft_wrap (
  output          inData_0_ce,
  output          inData_1_ce,
  output          inData_2_ce,
  output          inData_3_ce,

  input   [31:0]  inData_0,
  input   [31:0]  inData_1,
  input   [31:0]  inData_2,
  input   [31:0]  inData_3,

  output          outData_0_we,
  output          outData_1_we,
  output          outData_2_we,
  output          outData_3_we,  

  output  [41:0]  outData_0,
  output  [41:0]  outData_1,
  output  [41:0]  outData_2,
  output  [41:0]  outData_3,
  
  input           clk,
  input           rst,
  input           start,
  output          done,
  output          idle,
  output          ready

);
  1. Simulate the top level project

Click Run Simulation from Flow Navigator and select Run Behavioral Simulation. Vivado simulator launches with waveform loaded. The input data bus width is 32-bit and output data bus width is 42-bit.

If no issues are encountered, simulation ends smoothly.

Result verification SUCCEED!
Simulation finished.

Below is the screenshot of the simulation waveform.

../../_images/xsim_result.png

Close the simulation window.

At this point the tutorial is complete. You can Run Implementation from Flow Navigator panel and click OK in the pop-up window. This runs through the Vivado synthesis and implementation flow that generates both timing and resource reports for this IP.