High-Level Synthesis (HLS) is a key part of the Vitis development flow. The tool is responsible for compiling C/C++ code into an RTL module for implementation in the programmable logic (PL) region of AMD devices or platforms.
In the Vitis unified IDE the PL kernel is created as an HLS component, letting you run C simulation on your C/C++ source code, optimize your design with pragmas or directives, synthesize and analyze the results, and export the design as either an Vivado IP for use with the Vivado Design Suite, or as a Vitis kernel (
.xo) file for use in a higher-level System project.
The first step is to create a workspace for your project, and to launch the Vitis unified IDE using the following steps:
Create a workspace:
Launch the Vitis unified IDE:
vitis -w workDCT
The workspace is a folder for holding the various components and projects of a design.
TIP: The workspace is simply the place where you will store the files related to creating and building your project, or multiple projects.
The Vitis unified IDE opens displaying the Welcome page. Use the File > New Component > HLS to create a new HLS component. This opens the Create HLS Component wizard to the Name and Location page.
For the Component name field specify
For the Component location specify the workspace (default value)
Click Next to open the Configuration File page
The Configuration File lets you specify commands for building and running the HLS component as described in HLS Config File Commands. You can specify a new empty file, an existing config file, or generate a config file from an existing HLS project as described in Creating an HLS Component.
Select Empty File and click Next.
This opens the Source Files page.
In this tutorial, you are working with a simple discrete cosine transform (DCT) algorithm that processes an input matrix of values, applies fixed coefficients, and returns a matrix of modified values. In the
reference_files/src folder, the
dct.cpp contains the top-level DCT function.
Select the Add Files icon to open a file browser, navigate to
<tutorial_path>/Getting_Started/Vitis_HLS/reference_files/src/dct.cppand select Open to add the file.
Under the Top Function browse and select the
dct(short*, short*)function and click OK.
Under the Test Bench Files select the Add Files icon to open a file browser and select the following three files:
dct_test.cppis a test bench for the design that iterates through the kernel multiple times.
in.datprovides the input values to be processed by the kernel.
out.golden.datprovides known output results to use for comparing the output of the dct function against.
Writing a good testbench can greatly increase your productivity because C functions execute in orders of magnitude faster than RTL simulations. Using C to develop and validate the algorithm before synthesis is much faster than developing and debugging RTL code. For more information, refer to Writing a Testbench.
Click Next to open the the Select Part page to select the default part and click Next to open the Settings page.
On the Settings page, under
8nsfor the period, and
clock_uncertaintyto override the default values. The default clock uncertainty, when it is not specified, is 27% of the clock period. For more information, refer to Specifying the Clock Frequency
Vitis Kernel Flow Target, and specify
Generate a Vitis XOfor the
Click Next to open the Summary page. Review the Summary page and click Finish to create the defined HLS component.
The HLS component is created and opened as shown in the figure below.
In the Vitis Components Explorer you can see the
dct component created, with the
vitis-comp.json file opened in the center editor. You can see the
hls-config.cfg file which is where the build directives will be placed to control the simulation and synthesis process. You can also see the Sources folder and the Test Bench files that were added as the component was created.
The Flow Navigator displays the
dct component as the active component, and shows the flow for designing the HLS component including C Simulation, C Synthesis, C/RTL Co-simuation, Package, and Implementation. You will walk through some of these steps in the following sections.
You created the DCT project, targeted your AMD device or board, and configured the solution characteristics. You are ready to move to the next lab, Running Simulation, Synthesis and Analyzing Results.
Return to Main Page — Return to Start of Tutorial
Copyright © 2020–2023 Advanced Micro Devices, Inc