Here you use Vitis v++ tool to finish hardware linking and generate the .xclbin file. Execute following command:
make build_hw
This will execute v++ command with connectivity_x1.cfg as the linking configuration file. Find the following lines in the configuration file which instruct Vitis to connect GT transceivers specific signals for the xilinx_u200_gen3x16_xdma_1_202110_1 platform.
# For xilinx_u200_gen3x16_xdma_1_202110_1 platform
connect=eth0/clk_gt_freerun:ss_ucs/aclk_kernel_00
connect=io_clk_qsfp_refclka_00:eth0/gt_refclk
connect=eth0/gt_port:io_gt_qsfp_00
If you are using other cards or platforms, the signal/port names might be different, and you need to modify this accordingly. You can refer to the platform information reported by the platforminfo command for these platform specific GT signal/port naming. For example:
platforminfo -p xilinx_u200_gen3x16_xdma_1_202110_1 -v
After the v++ linking job finishes, you can use the Vivado GUI to open the Vivado project ./_x/link/vivado/vpl/prj/prj.xpr, then open the block design ulp. You can see that all the signals for the two kernels (with instance names df0 and eth0), especially those GT transceivers signals have been connected correctly, like following screenshot.
When v++ linking finishes, you will get the XCLBIN file top_level.xclbin. You could also use Vivado to open the project ./_x/link/vivado/vpl/prj/prj.xpr, and open the finally implemented design to review the reports and silicon floorplan.